A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate.

Integrated circuits (ICs 110) are attached to a wafer (120W). A stabilization layer (404) is formed over the wafer to strengthen the structure for further processing. Unlike a conventional mold compound, the stabilization layer is separated from at least some wafer areas around the ICs by one or more gap regions (450) to reduce the thermo-mechanical stress on the wafer and hence the wafer warpage. Alternatively or in addition, the stabilization layer can be a porous material having a low horizontal elastic modulus to reduce the wafer warpage, but having a high flexural modulus to reduce warpage and otherwise strengthen the structure for further processing. Other features and advantages are also provided.

A semiconductor device according to the present embodiment includes a circuit board comprising a plurality of electrodes provided on a first surface, a first resin layer provided on the first surface around the electrodes, and a second resin layer provided on the first resin layer. A first semiconductor chip is connected to a first one of the electrodes. A second semiconductor chip is provided above the first semiconductor chip, being larger than the first semiconductor chip, and is connected to a second one of the electrodes via a metal wire. A third resin layer is provided between the first semiconductor chip and the second semiconductor chip and between the second resin layer and the second semiconductor chip, and covers the first semiconductor chip.

Exemplified microscale selective laser sintering (μ-SLS or micro-SLS) systems and methods facilitate modeling of the nanoparticle powder bed by simulating the interactions between particles during the powder spreading operation. In particular, the exemplified methods and system use multiscale modeling techniques to accurately predict the formation and mechanical/electrical properties of parts produced by selective laser sintering of powder beds. Discrete element modeling is used for nanoscale particle interactions by implementing the different forces dominant at nanoscale. A heat transfer analysis is used to predict the sintering of individual particles in the powder beds in order to build up a complete structural model of the parts that are being produced by the SLS process.

A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use a film during fabrication to control the distribution of an under-fill material between one or more components and a packaging substrate. The method includes mounting components to a first side of a packaging substrate and applying a film to a second side of a packaging substrate. The method also includes mounting a lower component to the second side of the packaging substrate and under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent. The method also includes removing the film on the second side of the packaging substrate and mounting solder balls to the second side of the packaging substrate after removal of the film.

The present invention relates to an electrical assembly which has a conformal coating, wherein said conformal coating is obtainable by a method which comprises: (a) plasma polymerization of a compound of formula (I) and a fluorohydrocarbon, wherein the molar ratio of the compound of formula (I) to the fluorohydrocarbon is from 5:95 to 50:50, and deposition of the resulting polymer onto at least one surface of the electrical assembly: wherein: R.sub.1 represents C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; R.sub.2 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; R.sub.3 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; R.sub.4 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; R.sub.5 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; and R.sub.6 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl, and (b) plasma polymerization of a compound of formula (I) and deposition of the resulting polymer onto the polymer formed in step (a).

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A semiconductor device may be provided with: a semiconductor chip; an encapsulant encapsulating the semiconductor chip therein; and a conductor member joined to the semiconductor chip via a solder layer within the encapsulant. The conductor member may comprise a joint surface in contact with the solder layer and a side surface extending from a peripheral edge of the joint surface. The side surface may comprise an unroughened area and a roughened area that is greater in surface roughness than the unroughened area. The unroughened area may be located adjacent to the peripheral edge of the joint surface.

The present invention provides a flow guiding structure of chip, which comprises at least one flow guiding member disposed on a surface of a chip and adjacent to a plurality of connecting bumps disposed on the surface of the chip. When the chip is disposed on a board member, the at least one flow guiding member may guide the conductive medium on the surface of the chip to flow toward the connecting bumps and drive a plurality of conductive particles of the conductive medium to move toward the connecting bumps and thus increasing the number of the conductive particles on the surfaces of the connecting bumps. Alternatively, the flow guiding member may retard the flow of the conductive medium for avoiding the conductive particles from leaving the surfaces of the connecting bumps and thus preventing reduction of the number of the conductive particles on the surfaces of the connecting bumps.

An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surfaceof the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.