H01L2224/831

3D die stacking structure with fine pitches

A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.

Method of manufacturing semiconductor devices
10825795 · 2020-11-03 · ·

A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.

Method of manufacturing semiconductor devices
10825795 · 2020-11-03 · ·

A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.

Methods of forming power electronic assemblies using metal inverse opals and cap structures

Methods for forming bonded assemblies using metal inverse opal and cap structures are disclosed. In one embodiment, a method for forming a bonded assembly includes positioning a substrate against a polymer support that is porous, depositing a metal onto and within the polymer support, disposing a cap layer to the polymer support opposite of the substrate to form a bottom electrode, and removing the polymer support from between the substrate and the cap layer to form a metal inverse opal structure disposed therebetween.

Methods of forming power electronic assemblies using metal inverse opals and cap structures

Methods for forming bonded assemblies using metal inverse opal and cap structures are disclosed. In one embodiment, a method for forming a bonded assembly includes positioning a substrate against a polymer support that is porous, depositing a metal onto and within the polymer support, disposing a cap layer to the polymer support opposite of the substrate to form a bottom electrode, and removing the polymer support from between the substrate and the cap layer to form a metal inverse opal structure disposed therebetween.

Assembly process for circuit carrier and circuit carrier
20200294867 · 2020-09-17 ·

The invention concerns a process for the production of a circuit carrier (1) equipped with at least one surface-mount LED (SMD-LED), wherein the at least one SMD-LED (2) is positioned in oriented relationship to one or more reference points (3) of the circuit carrier (1) on the circuit carrier (1), wherein the position of a light-emitting region (4) of the at least one SMD-LED (2) is optically detected in the SMD-LED (2) and the at least one SMD-LED (2) is mounted to the circuit carrier (1) in dependence on the detected position of the light-emitting region (4) of the at least one SMD-LED (2), and such a circuit carrier (1).

Assembly process for circuit carrier and circuit carrier
20200294867 · 2020-09-17 ·

The invention concerns a process for the production of a circuit carrier (1) equipped with at least one surface-mount LED (SMD-LED), wherein the at least one SMD-LED (2) is positioned in oriented relationship to one or more reference points (3) of the circuit carrier (1) on the circuit carrier (1), wherein the position of a light-emitting region (4) of the at least one SMD-LED (2) is optically detected in the SMD-LED (2) and the at least one SMD-LED (2) is mounted to the circuit carrier (1) in dependence on the detected position of the light-emitting region (4) of the at least one SMD-LED (2), and such a circuit carrier (1).

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Under-fill deflash for a dual-sided ball grid array package
10770312 · 2020-09-08 · ·

Described herein methods of manufacturing dual-sided packaged electronic modules that control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include under-filling one or more components and deflashing a portion of the under-fill to remove under-fill material prior to attaching solder balls. The deflashing step removes a thin layer of under-fill material that may have coated contact pads for the ball grid array. Because the solder balls are not present during under-fill, there is little capillary action drawing material away from the components being under-filled. This can reduce the frequency of voids under the components being under-filled. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using under-fill deflash prior to attaching solder balls of the ball grid array.