H01L2224/831

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Systems of bonded substrates and methods for bonding substrates with bonding layers

A system of bonded substrates may include a first substrate, a second substrate, and a bonding layer. The first substrate may include a bonding surface, wherein a geometry of the bonding surface of the first substrate includes a plurality of microchannels. The second substrate may include a complementary bonding surface. The bonding layer may be positioned between the first substrate and the second substrate, wherein the bonding layer may fill the microchannels of the first substrate and may contact substantially the entire bonding surface of the first substrate. The bonding layer may include a metal.

Patterning polymer layer to reduce stress

A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.

SEMICONDUCTOR PACKAGE WITH SEALED THERMAL INTERFACE CAVITY WITH LOW THERMAL RESISTANCE LIQUID THERMAL INTERFACE MATERIAL
20190393118 · 2019-12-26 ·

A package is disclosed. The package includes a substrate, a die on the substrate, an integrated heat spreader on the substrate that encloses the die, the integrated heat spreader including a hole that extends through the integrated heat spreader, an air permeable adhesive contacting the integrated heat spreader and forming a cavity underneath the integrated heat spreader, and a liquid metal thermal interface material filling the cavity. A sealant plugs the hole that extends through the integrated heat spreader.

SEMICONDUCTOR PACKAGE WITH SEALED THERMAL INTERFACE CAVITY WITH LOW THERMAL RESISTANCE LIQUID THERMAL INTERFACE MATERIAL
20190393118 · 2019-12-26 ·

A package is disclosed. The package includes a substrate, a die on the substrate, an integrated heat spreader on the substrate that encloses the die, the integrated heat spreader including a hole that extends through the integrated heat spreader, an air permeable adhesive contacting the integrated heat spreader and forming a cavity underneath the integrated heat spreader, and a liquid metal thermal interface material filling the cavity. A sealant plugs the hole that extends through the integrated heat spreader.

INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Stretchable display module and manufacturing method thereof

A stretchable display module and a manufacturing method thereof are provided. The stretchable display module includes a display layer including a plurality of display islands arranged and spaced apart from each other, wherein two of the adjacent display islands are electrically connected by a connecting wire; a transparent adhesive layer including a filling adhesive layer filled in a spacing region between the display islands, a first adhesive layer disposed on a surface of the display layer opposite an emitting direction of the display layer, and a second adhesive layer disposed on a surface of the display layer in the emitting direction.

MICROELECTRONIC ASSEMBLIES HAVING CONDUCTIVE STRUCTURES WITH DIFFERENT THICKNESSES ON A CORE SUBSTRATE

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

MICROELECTRONIC ASSEMBLIES HAVING CONDUCTIVE STRUCTURES WITH DIFFERENT THICKNESSES ON A CORE SUBSTRATE

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.