A chip package structure and a method for producing the same are provided. The method at least includes: providing a substrate; placing a chip upside-down on the substrate; forming bonding wires coupled with the chip and the substrate; providing at least one reflecting member on an upper surface of the substrate, forming a support body on the substrate to cover the at least one reflecting member; providing a package cover adhered to the support body by a glass adhesive; performing a solidifying process in which a solidifying light beam is emitted to the reflecting member and the reflecting member reflects the solidifying light beam to the glass adhesive to solidify the glass adhesive; performing a packaging process in which a package body is formed to cover an edge surface of the package cover and a top part of the support body.

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A magnetic polymer for use in microelectronic fabrication includes a polymer matrix and a plurality of ferromagnetic particles disposed in the polymer matrix. The magnetic polymer can be part of an insulation layer in an inductor formed in one or more backend wiring layers of an integrated device. The magnetic polymer can also be in the form of a magnetic epoxy layer for mounting contacts of the integrated device to a package substrate.

A semiconductor device includes a semiconductor element and an electrically conductive member. The semiconductor element is configured to allow an electric current to flow from a first electrode to a second electrode and prevent an electric current flowing from the second electrode to the first electrode. The electrically conductive member is joined with the second electrode via a solder joint layer. Surface of the second electrode in contact with the solder joint layer mainly comprises nickel, and surface of the electrically conductive member in contact with the solder joint layer mainly comprises copper. The solder joint layer comprises first and second compound layers. The first compound layer is located at an interface with, the second electrode and comprises nickel-tin based intermetallic compound. The second compound layer is located at an interface with the electrically conductive member and comprises copper-tin based intermetallic compound.

A semiconductor device includes a semiconductor element and an electrically conductive member. The semiconductor element is configured to allow an electric current to flow from a first electrode to a second electrode and prevent an electric current flowing from the second electrode to the first electrode. The electrically conductive member is joined with the second electrode via a solder joint layer. Surface of the second electrode in contact with the solder joint layer mainly comprises nickel, and surface of the electrically conductive member in contact with the solder joint layer mainly comprises copper. The solder joint layer comprises first and second compound layers. The first compound layer is located at an interface with, the second electrode and comprises nickel-tin based intermetallic compound. The second compound layer is located at an interface with the electrically conductive member and comprises copper-tin based intermetallic compound.