A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

An object of the present invention is to provide a semiconductor device in which peeling between a mold resin and a substrate is suppressed. A semiconductor device 1 includes a semiconductor chip 20 and a substrate 10 that are molded with a mold resin layer 40. The semiconductor device 1 includes a resin layer 50 having a thickness of 200 nm or less different from the mold resin layer 40 between the cured mold resin layer 40 and the substrate 10. The resin layer 50 present between the mold resin layer 40 and the substrate 10 is preferably present on a periphery of 30% or more of the chip when an entire peripheral length of the chip is 100%.

An object of the present invention is to provide a semiconductor device in which peeling between a mold resin and a substrate is suppressed. A semiconductor device 1 includes a semiconductor chip 20 and a substrate 10 that are molded with a mold resin layer 40. The semiconductor device 1 includes a resin layer 50 having a thickness of 200 nm or less different from the mold resin layer 40 between the cured mold resin layer 40 and the substrate 10. The resin layer 50 present between the mold resin layer 40 and the substrate 10 is preferably present on a periphery of 30% or more of the chip when an entire peripheral length of the chip is 100%.

An electronic-component-mounted module has an electronic component, a first silver-sintered bonding layer bonded on one surface of the electronic component, a circuit layer made of copper or copper alloy and bonded on the first silver-sintered bonding layer, and a ceramic substrate board bonded on the circuit layer, and further has an insulation circuit substrate board with smaller linear expansion coefficient than the electronic component, a second silver-sintered bonding layer bonded on the other surface of the electronic component, and a lead frame with smaller linear expansion coefficient than the electronic component bonded on the second silver-sintered bonding layer; and a difference in the linear expansion coefficient between the insulation circuit substrate board and the lead frame is not more than 5 ppm/° C.

A semiconductor device includes a power semiconductor device, a circuit board, and an insulating substrate. The power semiconductor device includes contact pads. Adjacent ones of the contact pads are separated by one of a plurality of gaps. The circuit board includes traces for coupling with the contact pads of the power semiconductor device. The contact pads are physically attached to the traces. The insulating substrate is disposed between the circuit board and the power semiconductor device, where portions of the insulating substrate are disposed in the plurality of gaps, and where the insulating substrate has a monolithic structure.

A semiconductor device includes a power semiconductor device, a circuit board, and an insulating substrate. The power semiconductor device includes contact pads. Adjacent ones of the contact pads are separated by one of a plurality of gaps. The circuit board includes traces for coupling with the contact pads of the power semiconductor device. The contact pads are physically attached to the traces. The insulating substrate is disposed between the circuit board and the power semiconductor device, where portions of the insulating substrate are disposed in the plurality of gaps, and where the insulating substrate has a monolithic structure.

In a method for manufacturing a semiconductor device, a plurality of first provisional fixing portions are supplied on a front surface of a substrate such that the plurality of first provisional fixing portions are spaced from each other and thus dispersed. A first solder layer processed into a plate to be a first soldering portion is disposed in contact with the plurality of first provisional fixing portions. A semiconductor chip is disposed on the first solder layer. In addition a conductive member in the form of a flat plate is disposed thereon via a second provisional fixing portion and a second solder layer. A reflow process is performed to solder the substrate, the semiconductor chip and the conductive member together.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

An electronic device comprising: an array substrate having a first electrode and a second electrode; a first connecting member arranged on the first electrode; a first LED chip mounted on the first connecting member; a second connecting member arranged on the second electrode and being thicker than the first connecting member; and a second LED chip mounted on the second connecting member. A distance from a reference surface of the array substrate to a top surface of the second connecting member is larger than a distance from the reference surface to a top surface of the first connecting member.

A semiconductor device may be provided with a first member, a second member joined to a first region of the first member via a first solder layer and a third member joined to a second region of the first member via a second solder layer. The first region and the second region are located on one side of the first member. The first solder layer contains a plurality of support particles that is constituted of a material having a higher melting point than the first solder layer. The second solder layer does not contain any support particles.