An apparatus and method for measuring loop height of overlapping bonded wires, interconnecting the pads of a single or stacked silicon chips to the pads of a substrate taking the steps of: focussing of an optical assembly at multiple points of the bond wire including overlapping bond wires, capturing an image of the bond wire at each of the predetermined focused points; calculating the height of each point of the wire with respect to a reference plane; and tabulating the height data using the X, Y and Z coordinates.

There is provided a novel Cu bonding wire that achieves a favorable FAB shape and reduces a galvanic corrosion in a high-temperature environment to achieve a favorable bond reliability of the 2nd bonding part. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of 90 atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.0 or less where X is defined as an average value of a ratio of a Pd concentration C.sub.Pd (atomic %) to an Ni concentration C.sub.Ni (atomic %), C.sub.Pd/C.sub.Ni, for all measurement points in the coating layer, and the total number of measurement points in the coating layer whose absolute deviation from the average value X is 0.3X or less is 50% or more relative to the total number of measurement points in the coating layer.

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

An object of the present invention is to accurately measure the heights of wire loops densely disposed in a power module. A semiconductor manufacturing inspection system includes: an single-color illumination unit including a plurality of LED chips to emit light beams to a plurality of wire loops connected to surfaces of semiconductor elements; a camera to capture images of the wire loops; and an image processor to recognize an imaging region of each of the wire loops from the images, based on a luminance value and to measure the height of each of the wire loops based on the imaging region of the wire loop in the images. The LED chips emit the light beams to the separate wire loops, and the light beams emitted from two of the LED chips to adjacent two of the wire loops differ in luminance.

A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.

In a method for manufacturing a semiconductor device, a back surface of each of plurality of current-carrying semiconductor elements each having a plurality of P-N junction diodes built-in is connected to a first principal surface of a conductor plate. Further, a conductor piece is connected to a front surface of each of the plurality of current-carrying semiconductor elements. Then, a current-carrying test is conducted on the plurality of P-N junction diodes with a second principal surface of the conductor plate exposed on a bottom surface of an intermediate product of a semiconductor device including the plurality of current-carrying semiconductor elements, the conductor plate, and the conductor piece.

This wire shape inspecting apparatus comprises a camera which captures an image of a wire from above, a light which illuminates the wire from above, and a control unit, wherein the control unit performs: an inspection image acquiring process of acquiring a plurality of inspection images by causing the camera to capture images of the wire a plurality of times while changing a focal distance; and a first shape detecting process of identifying, in each inspection image, a light emitting portion, which is an image part including reflected light comprising light from the light that has been reflected by the wire, and identifying an actual light emitting portion position, which is the actual position of the light emitting portion, on the basis of the position of the light emitting portion in the inspection image and the focal distance when the inspection image was acquired.

A wire bonding method includes bonding a tip of a wire provided through a clamp and a capillary onto a bonding pad of a chip, moving the capillary to a connection pad of a substrate corresponding to the bonding pad, bonding the wire to the connection pad to form a bonding wire connecting the bonding pad to the connection pad, before the capillary is raised from the connection pad, applying a electrical signal to the wire to detect whether the wire and the connection pad are in contact with each other, changing a state of the clamp to a closed state when the wire is not in contact with the connection pad and maintaining the state of the clamp in an open state when the wire is in contact with the connection pad, and raising the capillary from the connection pad while maintaining the state of the clamp.

A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.