A display device includes a substrate including a display area having a plurality of pixel areas and a non-display area located at at least one side of the display area; a pixel in each of the pixel areas; and a plurality of fan-out lines in the non-display area to form a first conductive layer. The pixel includes a pixel circuit layer including at least one transistor and a first bridge line and a second bridge line; and a display element layer on the pixel circuit layer. Each of the first and second bridge lines is electrically connected to a corresponding fan-out line from among the fan-out lines.

A light-emitting diode (LED) chip includes a semiconductor epitaxial structure, an insulating substrate, a first metal layer, and a second metal layer. The semiconductor epitaxial structure includes a first semiconductor epitaxial layer, a second semiconductor epitaxial layer, and a light-emitting layer interposed between the first semiconductor epitaxial layer and the second semiconductor epitaxial layer. The insulating substrate has two opposite surfaces, and the first and second metal layers are respectively disposed on the two surfaces of the insulating substrate. An LED device and an LED lamp including the LED chip are also disclosed.

A semiconductor device and a manufacturing method thereof are provided. A semiconductor device includes a first semiconductor die, a second semiconductor die, a bonding layer, and a through die via. The first semiconductor die includes a first semiconductor substrate and a first conductive pad exposed at an active surface of the first semiconductor die. The second semiconductor die includes a second semiconductor substrate and a second conductive pad exposed at an active surface of the second semiconductor die. The first semiconductor die is stacked over the second semiconductor die. The bonding layer is disposed between the first and the second semiconductor die. The through die via electrically connects the first semiconductor die and the second semiconductor die. The through die via is embedded in the first semiconductor substrate, penetrates through the first conductive pad and the bonding layer, and reaches the second conductive pad.

A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.

A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

A semiconductor device includes a die stack and an encapsulant covering the die stack. The die stack includes a first die and a second die stacked upon one another, a bonding dielectric layer, and a through die via providing a vertical connection in the die stack. The first die includes a first substrate and a first conductive pad on the first substrate, and the second die includes a second substrate and a second conductive pad on the second substrate. The bonding dielectric layer interposed between the first substrate and the second substrate is in physical contact with at least one selected from the group of the first conductive pad and the second conductive pad. The through die via extends through the first conductive pad and the bonding dielectric layer and lands on the second pad.

A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.