A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element including a magnetic body is electrically connected to the second conductive elements. The semiconductor package body or the energy storage element has a plurality of first conductive elements to be electrically connected to an outside device. The three-dimensional package structure is applicable to a POL, (Point of Load) converter.

The invention relates to a method for producing a structured coating on a substrate, wherein the method comprises the following steps: providing a substrate having a surface to be coated and producing a structured coating on the surface of the substrate to be coated by depositing at least one evaporation coating material, namely aluminium oxide, silicon dioxide, silicon nitride, or titanium dioxide, on the surface of the substrate to be coated by means of thermal evaporation of the at least one evaporation coating material and using additive structuring. The invention further relates to a coated substrate and a semi-finished product having a coated substrate.

A power electronics module includes a substrate with a substrate metallization layer, which is separated into conducting areas for providing conducting paths for the power electronics module; a semiconductor switch chip bonded with a first power electrode to a first conducting area of the substrate metallization layer; a conductor plate bonded to a second power electrode of the semiconductor switch chip opposite to the first power electrode.

Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.

Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.

Disclosed are embodiments of a lower integrated circuit (IC) package structure for a package-on-package (PoP) assembly. The lower IC package structure includes an interposer having pads to mate with terminals of an upper IC package. An encapsulant material is disposed in the lower IC package, and this encapsulant may be disposed proximate one or more IC die. An upper IC package may be coupled with the lower IC package to form a PoP assembly. Such a PoP assembly may be disposed on a mainboard or other circuit board, and may form part of a computing system. Other embodiments are described and claimed.

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Disclosed herein are electrically conductive and hermetic vias disposed within an insulator substrate of a feedthrough assembly and methods for making and using the same. Such aspects of the present invention consequently provide for the miniaturization of feedthrough assemblies inasmuch as the feedthrough components of the present invention are capable of supporting very small and hermetic conductively filled via holes in the absence of additional components, such as, for example, terminal pins, leadwires, and the like.

Multi-chip modules may include stacked semiconductor devices having spacers therebetween. Discrete conductive elements may extend over the active surface of an underlying semiconductor device from respective bond pads of the underlying semiconductor device, through a space formed by the spacers, to respective contact areas on a substrate. Each discrete conductive element extending through two side openings opposite one another may extend from a respective centrally located bond pad proximate to a central portion of the active surface of the underlying semiconductor device. Each discrete conductive element extending through another, perpendicular opening may extend from a respective peripheral bond pad located proximate to a peripheral portion of the active surface of the underlying semiconductor device.

An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.