Systems and methods of manufacture are disclosed for a semiconductor device assembly having a semiconductor device having a first side and a second side opposite of the first side, a mold compound region adjacent to the semiconductor device, a redistribution layer adjacent to the first side of the semiconductor device, a dielectric layer adjacent to the second side of the semiconductor device, a first via extending through the mold compound region that connects to at least one trace in the dielectric layer, and an antenna structure formed on the dielectric layer and connected to the semiconductor device through the first via.

Embodiments discussed herein refer to systems and structures for focusing dispersal of electromagnetic signals. Focusing of the electromagnetic signals is achieved by a reflective lens that is constructed from several extremely high frequency focusing layers. Each focusing layer can include an extremely high frequency focusing window that, collectively, define the geometry of a cavity backed reflective lens and its ability to focus electromagnetic signal dispersion.

An electronic device including an antenna module is provided. The electronic device includes a 5th generation (5G) antenna module that includes an antenna array, at least one conductive region operating as a ground with respect to the antenna array, and a first communication circuit feeding a power to the antenna array to communicate through a millimeter wave signal, and a printed circuit board (PCB) that includes a second communication circuit and a ground region. The second communication circuit feeds the power to an electrical path at least including the at least one conductive region and transmits or receives a signal in a frequency band different from a frequency band of the millimeter wave signal based on the electrical path supplied with the power and the ground region.

An antenna module that includes an antenna substrate, a plurality of three-dimensional (3-D) antenna cells on a first surface of the antenna substrate, a plurality of packaged circuitry on a second surface of the antenna substrate, and a plurality of supporting balls mounted on the second surface of the antenna substrate. The plurality of packaged circuitry includes a plurality of radio-frequency (RF) chips on the second surface of the antenna substrate. Each of the plurality of 3-D antenna cells comprises a raised antenna patch with a plurality of projections and a plurality of supporting legs, where at least a relief cut is provided between one of the plurality of projections and one of the plurality of supporting legs.

Restrictions in placement of an antenna for performing transmission and reception of a signal by wireless communication when the antenna is used together with a CSP (Chip Size Package) are eliminated. A semiconductor device includes a chip size package and a substrate. The chip size package includes a semiconductor element. Further, the chip size package includes a connection portion that electrically connects the semiconductor element and an outside to each other. The substrate includes an antenna connected to the connection portion of the chip size package for performing transmission and reception of a signal by wireless communication. With this configuration, the semiconductor device performs transmission and reception of a signal to and from the outside through the antenna provided on the substrate.

An antenna module includes a dielectric substrate, in or on which a feed element is formed, a dielectric substrate, in which a ground electrode (GND) is formed, and conductive members. The dielectric substrate is disposed opposite the dielectric substrate. When viewed in plan in the direction normal to the feed element, the conductive members are disposed around the feed element. An air layer is formed between the dielectric substrate and the dielectric substrate. The conductive members are formed in the air layer.

Various embodiments may provide a semiconductor package. The semiconductor package may include a semiconductor chip, a first mold compound layer at least partially covering the semiconductor chip, and a redistribution layer over the first mold compound layer, the redistribution layer including one or more electrically conductive lines in electrical connection with the semiconductor chip. The semiconductor package may additionally include a second mold compound layer over the redistribution layer, and an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines.

A wave phased array is manufactured using additive manufacturing technology (AMT). The wave phased array includes a radiator, a radiator dilation layer supporting the radiator, a beamformer supporting the radiator dilation layer, a beamformer dilation layer supporting the beamformer, and a substrate support layer supporting the beamformer dilation layer. At least one of the radiator, the radiator dilation layer, the beamformer, the beamformer dilation layer and the substrate support layer is fabricated at least in part by an AMT process.

A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.