A distributed power amplifier includes radio frequency (RF) input and output terminals. A first field effect transistor (FET) is coupled at a first gate terminal to the RF input terminal and at a first drain terminal to the RF output terminal. The first FET has a first periphery and a first source terminal electrically connected to ground potential. A second FET has a second periphery smaller than the first periphery. The second FET has a second gate terminal electrically coupled to the first gate terminal through a first inductor, a second drain terminal electrically coupled to the first drain terminal through a second inductor, and a second source terminal electrically connected to the ground potential. A drain voltage terminal, which excludes a resistive element, is electrically coupled to a drain bias network through which a drain bias voltage is applied to the first drain terminal and the second drain terminal.

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

In some embodiments, an amplifier system can include an amplifier circuit having first and second amplifiers configured to amplify respective first and second portions of an input signal. Each of the first and second amplifiers can include a cascode stage with input and output transistors arranged in a cascode configuration. The amplifier system can further include an envelope tracking bias circuit coupled to the amplifier circuit and configured to provide a bias signal to the output transistor of the cascode stage of at least one of the first and second amplifiers. The amplifier system can further include a supply circuit configured to provide a non-envelope tracking supply voltage to the output transistor of the cascode stage of the at least one of the first and second amplifiers.

Example embodiments relate to lead frame based molded radio frequency packages. One example package includes a substrate. The package also includes a first electrical component arranged on the substrate. Additionally, the package includes a second electrical component. Further, the package includes a plurality of leads that are arranged spaced apart from the substrate and fixed in position relative thereto by a solidified molding compound. The leads were part of a lead frame prior to separating the package from the lead frame. The substrate was physically and electrically connected to the lead frame using a plurality of spaced apart connecting members prior to separating the package from the lead frame. During the separating of the package from the lead frame, each connecting member was divided into a first connecting member part and a second connecting member part. In addition, the package includes a frame part.

A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

Adaptive bias networks include small transistors connected to adjust gate bias voltage of one or more transistors of an amplifier or amplifier stage, or in a main or auxiliary path of a compound amplifier such as a Doherty amplifier. The small transistors are sized to avoid additional loading of the input. The adaptive bias circuits of preferred embodiments adjust the gate bias to produce a boost in gate bias voltage of an nFET transistor when the input power is in an upper portion of the amplifier or amplifier stage's input power range, thereby increasing the gain, and reduce gate bias voltage of a pFET transistor in the upper portion of the amplifier's input power range, thereby also increasing the gain. The adaptive bias networks can be implemented with varactors to vary DC voltage across the varactor to change its capacitance and compensate changing input capacitance of the amplifier input FET.

A Doherty amplifier includes: a first amplifying element to amplify a first signal; a second amplifying element to amplify a second signal having a phase difference with the first signal; a first transmission line connected to an output terminal of the first amplifying element; and a second transmission line connected to an output terminal of the second amplifying element, wherein the first transmission line and the second transmission line are equal to each other in characteristic impedance, the phase difference between the first signal and the second signal is not equal to a difference in electrical length between the second transmission line and the first transmission line, and the first signal having passed through the first transmission line and the second signal having passed through the second transmission line are subjected to different phase synthesis.

A Doherty amplifier includes a first amplifier that includes first output fingers and a first output electrode connected to the first output fingers, a second amplifier that includes second output fingers and a second output electrode connected to the second output fingers, a first bonding wire connected between a first region in the first output electrode and a second region in the second output electrode, a second bonding wire connected between a third region in the first output electrode and a fourth region in the second output electrode, and at least one of a first capacitor connected in series with the first bonding wire, and a second capacitor connected in parallel with the second bonding wire, wherein the first and the third regions are regions to which the first output fingers are connected, and the second and the fourth regions are regions to which second output fingers are connected.

A radio frequency power amplifier with harmonic control circuit as well as method for manufacturing the same are disclosed. According to an embodiment, a radio frequency power amplifier includes: a planar dielectric substrate, a first conductive layer and a second conducting layer. The first conductive layer is disposed on a first side of the planar dielectric substrate. The second conducting layer is disposed on a second side of the planar dielectric substrate. The first conductive layer has a pattern comprising one or more harmonic control circuits. The second conductive layer acts as a ground plane. The second side of the planar dielectric substrate is opposite to the first side of the planar dielectric substrate.

In accordance with an aspect of the present disclosure, there is provided a power amplification apparatus, the apparatus comprising: an input part; a first-1 transformer and a first-2 transformer connected to the input part in parallel; a first amplifier and a second amplifier connected to the first-1 transformer and the first-2 transformer, respectively; a first switch connected to one side of the first-2 transformer; a second-1 transformer and a second-2 transformer connected to the first amplifier and the second amplifier, respectively, and connected to an output part in parallel; and a second switch connected to one side of the second-2 transformer.