A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuits.

Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor with a drain-source capacitance that is relatively low, an input impedance matching circuit, and an input-side harmonic termination circuit. The input impedance matching circuit includes a harmonic termination circuit, which in turn includes a first inductance (a first plurality of bondwires) and a first capacitance coupled in series between the transistor output and a ground reference node. The input impedance matching circuit also includes a second inductance (a second plurality of bondwires), a third inductance (a third plurality of bondwires), and a second capacitance coupled in a T-match configuration between the input lead and the transistor input. The first and second capacitances may be metal-insulator-metal capacitors in an integrated passive device.

One embodiment describes a transimpedance amplifier (TIA) system. The system includes a transistor arranged between an input node and an output node to set an amplitude of an output voltage at the output node based on an amplitude of an input current signal provided at the input node. The system also includes a negative feedback transformer coupled to the transistor to provide a negative feedback gain with respect to the output voltage to substantially increase transconductance of the transistor.

A variable resistance element is connected between a first input terminal of a first amplifier and a second input terminal of a second amplifier, and has a resistance value between the first input terminal and the second input terminal that is varied according to an amplitude value of a first voltage signal or an amplitude value or a differential voltage signal. A variable current source is connected between the first input terminal and a ground, and controls a current value of a current flowing to the ground from the first input terminal according to a value of an offset of the differential voltage signal. A bias voltage having the same value as that of a bias voltage that is applied to the first input terminal is applied to the second input terminal.

The present disclosure provides a receiving circuit for adaptive impedance matching and an operating method thereof. The receiving circuit includes: a first amplification module configured to amplify an input signal input from an input end of the first amplification module to generate a first amplified signal; a frequency mixing module, an input end of which is connected to an output end of the first amplification module, and configured to down-convert the first amplified signal to generate a down-converted signal; and a second amplification module, an input end of which is connected to an output end of the frequency mixing module, and configured to amplify the down-converted signal to generate an output signal, wherein the first amplification module includes an active negative feedback structure for providing adaptive impedance matching in a first bandwidth range.

This invention relates to a self-excited oscillation suppression device and method for the power amplifying circuit, belonging to the field of electronic technology. Said power amplifying circuit includes a FET and a feedback loop. Said device includes: a first compensation circuit which is connected between a drain and a gate of the FET and a second compensation circuit which is connected in parallel with a feedback resistor of said feedback loop. It can solve self-excited oscillation caused by deep negative feedback in the existing power amplifying circuit. The first compensation circuit can shift the open-loop gain curve forward as a whole, and the second compensation circuit can speed up the closure of the feedback gain curve and the open-loop gain curve so that the two curves will close up before the self-excited oscillation; the self-excited oscillation will be suppressed, and the stability of the power amplifying circuit will be improved.

There are an amplifier circuit which includes a first current source that is connected to a power supply line to which a first electric potential is supplied, a differential input circuit that is connected between the first current source and a first node and configured to receive a differential input signal, a second current source that is connected between a power supply line to which a second electric potential is supplied and the first node, and a load circuit that is connected between a power supply line to which the first electric potential is supplied and a second node, and an inductor circuit is further connected between the first node and the second node. Thereby, the amplifier circuit achieves both lower voltage and linearity.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor with a drain-source capacitance that is relatively low, an input impedance matching circuit, and an input-side harmonic termination circuit. The input impedance matching circuit includes a harmonic termination circuit, which in turn includes a first inductance (a first plurality of bondwires) and a first capacitance coupled in series between the transistor output and a ground reference node. The input impedance matching circuit also includes a second inductance (a second plurality of bondwires), a third inductance (a third plurality of bondwires), and a second capacitance coupled in a T-match configuration between the input lead and the transistor input. The first and second capacitances may be metal-insulator-metal capacitors in an integrated passive device.