The present disclosure relates to single-ended-to-differential amplifiers and radio frequency receivers. One example single-ended-to-differential amplifier includes a first inverting amplifier, a second inverting amplifier, and a third inverting amplifier. Both an input end of the first inverting amplifier and an input end of the second inverting amplifier are coupled to an input end of the single-ended-to-differential amplifier, an output end of the first inverting amplifier is coupled to an input end of the third inverting amplifier, an output end of the second inverting amplifier is coupled to a first output end of the single-ended-to-differential amplifier, and an output end of the third inverting amplifier is coupled to a second output end of the single-ended-to-differential amplifier. An impedance element is coupled between the input end of the first inverting amplifier and the output end of the first inverting amplifier.

Disclosed herein are methods for use in operating signal amplifiers that provide impedance adjustments for different gain modes. The impedance adjustments are configured to result in a constant real impedance for an input signal at the amplifier. Some of the disclosed methods adjust impedance using switchable inductors to compensate for changes in impedance with changing gain modes. Some of the disclosed methods adjust a device size to compensate for changes in impedance with changing gain modes. By providing impedance adjustments, the amplifiers reduce losses and improve performance by improving impedance matching over a range of gain modes.

An amplifier circuit includes an amplifier core having a cascode transistor and a gain transistor, a bias circuit coupled to the amplifier core, the bias circuit comprising: a first current source, a second current source, an operational transconductance amplifier (OTA), a bias cascode transistor pair having a bias cascode transistor and a bias gain transistor, and a replica circuit coupled to the first current source and to the second current source.

A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

Aspects of the present disclosure provide a circuit configured to adjust an input impedance of an amplifier such as a low-noise amplifier. In certain aspects, the circuit is coupled to a node, wherein the node is between a first transistor and a second transistor of the amplifier. The circuit may include an inductor and a capacitor coupled in series, wherein the inductor is coupled with one or more load inductors of the amplifier through negative magnetic coupling.

A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.

An amplifier circuit includes: a transistor provided between an input terminal and an output terminal and having a gate connected to the input terminal, a source connected to a ground, and a drain connected to the output terminal; an inductor connected between the source and the ground; an inductor connected between the gate and the input terminal, and switches connected to at least one of the inductors and configured to change a mutual inductance of the inductors.

Methods and devices for reducing gate node instability of a differential cascode amplifier are presented. Ground return loops, and therefore corresponding parasitic inductances, are eliminated by using voltage symmetry at nodes of two cascode amplification legs of the differential cascode amplifier. Series connected capacitors are coupled between gate nodes of pairs of cascode amplifiers of the two cascode amplification legs so to create a common node connecting the two capacitors. In order to reduce peak to peak voltage variation at the common node under large signal conditions, a shunting capacitor is connected to the common node.

A LNA (low-noise amplifier) includes a matching network configured to provide a three-way coupling between an input node, a matched node, and a source node; a gate capacitor configured to provide AC (alternate current) coupling between the matched node and a gate node; a cascode amplifier configured to receive a gate voltage at the gate node and output an output voltage at an output node in accordance with a source degeneration at the source node; and a load network connected to the output node, wherein the matching network having a shunt inductor and a series inductor that are overlapped in layout to have a strong mutual coupling and a source degenerating inductor that is laid out in a close proximity to the shunt inductor to have a strong mutual coupling

An amplifying circuit comprises: a plurality of first transistors; a second transistor coupled in series with the first transistor; and a compensation capacitor group comprising a plurality of compensation capacitors and a plurality of switches. When the amplifying circuit operates in a first gain mode, a first number of first transistors are turned on and a second number of compensation capacitors are coupled between the first terminal and the second terminal of the first transistor. When the amplifying circuit operates in a second gain mode, a third number of first transistors are turned on and a fourth number of compensation capacitors are coupled between the first terminal and the second terminal of the first transistor. The first number is larger than the third number, and the second number is larger than the fourth number.