Patent classifications
H03F1/308
Method and device for self-biased and self-regulated common-mode amplification
An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.
POWER AMPLIFIER
The present invention discloses a power amplifier capable of adaptively operating in one of an energy efficient mode and a high output power mode. An embodiment of the power amplifier includes a first transistor, a second transistor, a first bias element, a second bias element, a third bias element and a plurality of switches. In the energy efficient mode, by the control over the on/off states of the switches, an inverter type power amplifier is realized with the first transistor, the second transistor, the second bias element and the third bias element. In the high output power mode, by the control over the on/off states of the switches, a common source amplifier or a common emitter amplifier is realized with the second transistor and the first bias element.
METHOD AND DEVICE FOR SELF-BIASED AND SELF-REGULATED COMMON-MODE AMPLIFICATION
An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.
AMPLIFIER FOR CONTORLLING OUTPUT RANGE AND MULTI-STAGE AMPLIFICATION DEVICE USING THE SAME
An amplifier includes a differential amplification block suitable for receiving and amplifying a first differential input signal and a second differential input signal; an output block suitable for determining an output signal according to a state of amplified signals outputted from the differential amplification block; and an output range restriction block suitable for controlling an output range of the output signal outputted from the output block based on a maximum clamping signal and a minimum clamping signal.
High linearity inductorless LNA
An inductor-less low noise amplifier (LNA) with high linearity is disclosed. The low noise amplifier includes: an input signal stage receiving an input signal; a first amplifier configured to receive the input signal, generate a first amplification signal by amplifying the received input signal, and output the generated first amplification signal, as a first output signal, to a first output terminal; a second amplifier configured to receive the input signal, generate a second amplification signal by amplifying the received input signal, and output the generated second amplification signal, as a second output signal, to a second output terminal; an output signal stage outputting a superimposition signal obtained by superimposing the first output signal and the second output signal; a first resistor feeding back the superimposition signal to the input signal stage; and a switch connecting/disconnecting between the input signal stage and the output signal stage.
Class AB amplifier with bias control
An amplifier arrangement comprising first and second power amplifiers (T1, T2) having drains connected to positive and negative drive voltages, respectively, and gates connected to an input signal. The arrangement further comprises first and second current sensors (1, 2) for detecting first and second drain currents from the power amplifiers, processing circuitry (3) adapted to identify the smallest drain current, and a feedback control loop (5) and means for driving a bias current dependent on a feedback signal through a resistor connected between the input signal and the gate of an inactive one of the first and second power amplifiers. The control loop will keep the idle current constant in the transistor with the lowest current (the inactive transistor). Thereby, the current running in the transistor which does not deliver current to the load will be fixed at a desired value.
Memory effect reduction using low impedance biasing
A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.
CLASS AB AMPLIFIER WITH BIAS CONTROL
An amplifier arrangement comprising first and second power amplifiers (T1, T2) having drains connected to positive and negative drive voltages, respectively, and gates connected to an input signal. The arrangement further comprises first and second current sensors (1, 2) for detecting first and second drain currents from the power amplifiers, processing circuitry (3) adapted to identify the smallest drain current, and a feedback control loop (5) and means for driving a bias current dependent on a feedback signal through a resistor connected between the input signal and the gate of an inactive one of the first and second power amplifiers. The control loop will keep the idle current constant in the transistor with the lowest current (the inactive transistor). Thereby, the current running in the transistor which does not deliver current to the load will be fixed at a desired value.
Class-D amplifier
In a class-D amplifier, oscillation phenomenon is suppressed in a high RF range and surge voltage is reduced. An oscillation absorption circuit is connected on the power supply side of the class-D amplifier circuit, and the class-D amplifier circuit and thus connected oscillation absorption circuit equivalently configure an oscillation circuit. Resistance provided in the oscillation absorption circuit is assumed as damping resistance of the oscillation circuit, thereby suppressing the oscillation phenomenon and reducing the surge voltage. The oscillation absorption circuit is made up of the RL parallel circuit of resistance and inductance. The oscillation absorption circuit and the class-D amplifier circuit constitute the oscillation circuit, and the resistance of the oscillation absorption circuit constitutes the damping resistance of the oscillation circuit in the high RF range.
UNIT AMPLIFICATION CIRCUIT, AMPLIFIER AND RECEIVING CIRCUIT
A unit amplification circuit includes a push-pull circuit having a transistor with a gate connected to an input terminal, a symmetrical circuit connected symmetrically to the push-pull circuit and configured to be turned off in a first operation mode and turned on in a second operation mode, and a path control circuit connected to a drain of the transistor and configured to connect the drain and an output terminal in the first operation mode and to disconnect the drain and the output terminal in the second operation mode.