Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals. The power amplifier system further includes a supply modulator that controls a voltage level of a supply voltage of the power amplification stage based on the one or more detection signals such that the supply voltage is modulated with the output signal envelope through positive envelope feedback.

Provided are an input matching circuit, at least one amplifying transistor that receives a signal from the input matching circuit, a first dummy transistor that receives a signal from the input matching circuit, a second dummy transistor that receives a signal from the input matching circuit, and an output matching circuit that outputs an output of the amplifying transistor, the amplifying transistor being arranged between the first dummy transistor and the second dummy transistor, the amplifying transistor, the first dummy transistor, and the second dummy transistor being provided in a row along the input matching circuit.

Provided are an input matching circuit, at least one amplifying transistor that receives a signal from the input matching circuit, a first dummy transistor that receives a signal from the input matching circuit, a second dummy transistor that receives a signal from the input matching circuit, and an output matching circuit that outputs an output of the amplifying transistor, the amplifying transistor being arranged between the first dummy transistor and the second dummy transistor, the amplifying transistor, the first dummy transistor, and the second dummy transistor being provided in a row along the input matching circuit.

An apparatus comprising: a cascode arrangement comprising two or more transistors, the cascode arrangement coupled between a supply voltage terminal for receiving a supply voltage from a battery and a ground terminal, and a bias voltage generator configured to provide a bias voltage to at least one of the two or more transistors of the cascode arrangement to bias the cascode arrangement, the bias voltage generator further configured to increase the bias voltage with increasing supply voltage at a first rate over a first supply voltage range and increase the bias voltage with increasing supply voltage at a second rate, greater than the first rate, over a second supply voltage range, wherein the second supply voltage range comprises a range of voltages greater than the first supply voltage range.

An apparatus comprising: a cascode arrangement comprising two or more transistors, the cascode arrangement coupled between a supply voltage terminal for receiving a supply voltage from a battery and a ground terminal, and a bias voltage generator configured to provide a bias voltage to at least one of the two or more transistors of the cascode arrangement to bias the cascode arrangement, the bias voltage generator further configured to increase the bias voltage with increasing supply voltage at a first rate over a first supply voltage range and increase the bias voltage with increasing supply voltage at a second rate, greater than the first rate, over a second supply voltage range, wherein the second supply voltage range comprises a range of voltages greater than the first supply voltage range.

An RF amplifier utilizes first and second main amplifiers in a balanced amplifier configuration with first and second auxiliary amplifiers connected in parallel across the first and second main amplifiers, respectively. The main and the auxiliary amplifiers are biased such that the third-order nonlinearity components in the combined output current are reduced. A common or independent bias control circuit(s) control(s) the DC operating bias of the auxiliary amplifiers and establishes DC operating points on curves representing third-order nonlinear components within the drain current having a positive slope (opposite to the corresponding slope of the main amplifiers). This results in reduction of overall third-order nonlinear components in combined currents at the output. In another embodiment, a phase shift of an input to one auxiliary amplifier is used to provide a peak in minimization at a frequency associated with the phase shift.

Low noise amplifiers (LNAs) are disclosed herein. In certain embodiments, an LNA includes an input balun configured to convert a single-ended radio frequency (RF) receive signal to a differential RF receive signal, an amplifier chain configured to amplify the differential RF receive signal to generate a differential amplified RF receive signal, and an output balun configured to convert the differential amplified RF receive signal into a single-ended amplified RF receive signal. The LNA's amplifier chain is operable in multiple gain modes, and includes a first differential amplification stage, a second differential amplification stage, and a third differential amplification stage.

An interface circuit includes an input circuit. The input circuit includes a first input pin, a second input pin and a third input pin. The input circuit further includes a first operational amplifier including a first output pin, a first non-inverting input pin electrically coupled to the first input pin via a first impedance and a first switch, and a first inverting input pin coupled to the first output pin. The input circuit also includes a second operational amplifier including a second output pin, a second non-inverting input electrically coupled to the second input pin via a second impedance and a second inverting input pin electrically coupled to the third input pin via a third impedance and a second switch. The first input pin and the second input pin are electrically coupled via a third switch and a fourth impedance.

An interface circuit includes an input circuit. The input circuit includes a first input pin, a second input pin and a third input pin. The input circuit further includes a first operational amplifier including a first output pin, a first non-inverting input pin electrically coupled to the first input pin via a first impedance and a first switch, and a first inverting input pin coupled to the first output pin. The input circuit also includes a second operational amplifier including a second output pin, a second non-inverting input electrically coupled to the second input pin via a second impedance and a second inverting input pin electrically coupled to the third input pin via a third impedance and a second switch. The first input pin and the second input pin are electrically coupled via a third switch and a fourth impedance.

In one embodiment, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to a second frequency signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the second frequency signal, the PGA having a second controllable gain; a digitizer to digitize the second frequency signal to a digitized signal; a demodulator coupled to the digitizer to demodulate the digitized signal; an automatic gain control (AGC) circuit to control one or more of the first controllable gain and the second controllable gain; and an AGC settling circuit to cause the demodulator to begin operation in response to determining that the AGC circuit has settled.