An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate (i) a variable current and (ii) a constant current. The variable current may be proportional to a temperature of the first circuit. The second circuit may be configured to present a resistance through a plurality of first transistors between two ports in response to both the variable current and the constant current. The resistance may have a predefined dependence on the temperature.

A power amplifier (PA) cell is coupled to an input signal source an a load, and includes a transistor coupled to the load; a first inductor coupled to a gate of the transistor; and a second inductor coupled to a source of the transistor, wherein the first inductor and the second inductor each includes a first conductive coil and a second conductive coil, respectively, having first and second inductance values, respectively, such that the power cell is coupled to the input signal source without an input impedance matching circuit disposed between the gate of the transistor and the input signal source, and without an output impedance matching circuit disposed between a drain of the transistor and the load.

A power amplifier (PA) cell is coupled to an input signal source an a load, and includes a transistor coupled to the load; a first inductor coupled to a gate of the transistor; and a second inductor coupled to a source of the transistor, wherein the first inductor and the second inductor each includes a first conductive coil and a second conductive coil, respectively, having first and second inductance values, respectively, such that the power cell is coupled to the input signal source without an input impedance matching circuit disposed between the gate of the transistor and the input signal source, and without an output impedance matching circuit disposed between a drain of the transistor and the load.

An amplifier according to an embodiment of the present disclosure includes a first transistor and a first matching circuit. The first matching circuit is connected between an input terminal and a control terminal of the first transistor. A first terminal of the first transistor is connected to a ground. A second terminal of the first transistor is connected to a power supply and an output terminal. The first matching circuit includes a first inductor, a second inductor, and a first switch. The first inductor has an end connected to the control terminal. The second inductor has an end connected to the other end of the first inductor. The first switch is configured to selectively switch between electrical continuity between the input terminal and the other end of the first inductor and electrical continuity between the input terminal and the other end of the second inductor.

An amplifier according to an embodiment of the present disclosure includes a first transistor and a first matching circuit. The first matching circuit is connected between an input terminal and a control terminal of the first transistor. A first terminal of the first transistor is connected to a ground. A second terminal of the first transistor is connected to a power supply and an output terminal. The first matching circuit includes a first inductor, a second inductor, and a first switch. The first inductor has an end connected to the control terminal. The second inductor has an end connected to the other end of the first inductor. The first switch is configured to selectively switch between electrical continuity between the input terminal and the other end of the first inductor and electrical continuity between the input terminal and the other end of the second inductor.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

The addition of gate bias resistors substantially balances the voltage across any number of series-connected FETs, while the feedback control of the gate-source voltage of one FET controls the current through all of the FETs. In this way, the thermal load and voltage stress are substantially balanced for series connected FETs operating in active linear mode (partially on), enabling operation at voltages much higher than the individual ratings of low cost, readily available FETs. Alternatively, series-connecting FETs for active-mode operation is thermally equivalent to paralleling because the FET heat load is practically uniform, enabling operation at much higher current. This concept is extended to a series connection of FETs that can block, pass, and/or limit alternating load current with the voltage applied across all the FETs being either polarity or alternating polarity. We provide analysis, practical design considerations, and simulation results.