A power management circuit supporting phase correction in an analog signal is disclosed. The power management circuit includes a power amplifier circuit configured to amplify an analog signal having a time-variant power envelope based on a modulated voltage. The power management circuit also includes an envelope tracking (ET) integrated circuit (ETIC) configured to generate the modulated voltage and a modulated phase correction voltage to thereby cause a phase change in the analog signal. In embodiments disclosed herein, a correlation between the time-variant power envelope, the modulated voltage, and the modulated phase correction voltage is explored to thereby allow the ETIC to generate the modulated voltage and the modulated phase correction voltage based on the time-variant power envelope. As a result, it is possible to enable good time and phase alignment between the modulated voltage and the time-variant power envelope to thereby improve efficiency and linearity of the power amplifier circuit.

A power management circuit supporting phase correction in an analog signal is disclosed. The power management circuit includes a power amplifier circuit configured to amplify an analog signal having a time-variant power envelope based on a modulated voltage. The power management circuit also includes an envelope tracking (ET) integrated circuit (ETIC) configured to generate the modulated voltage and a modulated phase correction voltage to thereby cause a phase change in the analog signal. In embodiments disclosed herein, a correlation between the time-variant power envelope, the modulated voltage, and the modulated phase correction voltage is explored to thereby allow the ETIC to generate the modulated voltage and the modulated phase correction voltage based on the time-variant power envelope. As a result, it is possible to enable good time and phase alignment between the modulated voltage and the time-variant power envelope to thereby improve efficiency and linearity of the power amplifier circuit.

A semiconductor amplifier 1 includes transistors 21a and 21b mounted side by side on a bottom plate 2 in a space in a package 6, a matching circuit 22a mounted between the transistors 21a, 21b on the bottom plate 2, a matching circuit 22b mounted on an opposite side of the transistor 21b from the transistor 21a on the bottom plate 2, an input terminal T.sub.IN installed on one side of a wiring substrate 3, an output terminal T.sub.OUT installed on the other side of the wiring substrate 3, and gate bias terminals T.sub.1G and T.sub.2G and drain bias terminals T.sub.1D and T.sub.2D installed at positions with the input terminal T.sub.IN and the output terminal T.sub.OUT of the wiring substrate 3, and the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are linearly placed between the input terminal T.sub.IN and the output terminal T.sub.OUT.

Systems, devices, and methods related to hybrid basis function, neural network-based digital predistortion (DPD) are provided. An example apparatus for a radio frequency (RF) transceiver includes a digital predistortion (DPD) actuator to receive an input signal associated with a nonlinear component of the RF transceiver and output a predistorted signal. The DPD actuator includes a basis-function-based actuator to perform a first DPD operation using a set of basis functions associated with a first nonlinear characteristic of the nonlinear component. The DPD actuator further includes a neural network-based actuator to perform a second DPD operation using a first neural network associated with a second nonlinear characteristic of the nonlinear component. The predistorted signal is based on a first output signal of the basis-function-based actuator and a second output signal of the neural network-based actuator.

A power amplifier circuit includes a first power supply terminal electrically connected to a first power amplifier; a second power supply terminal electrically connected to a second power amplifier subsequent to the first power amplifier; a first external power supply line configured to electrically connect a power supply circuit configured to output a power supply potential corresponding to an amplitude level of a high-frequency input signal and the first power supply terminal; and a second external power supply line configured to electrically connect the power supply circuit and the second power supply terminal. An inductance value of the first external power supply line is higher than an inductance value of the second external power supply line.

A power amplifier circuit includes a first power supply terminal electrically connected to a first power amplifier; a second power supply terminal electrically connected to a second power amplifier subsequent to the first power amplifier; a first external power supply line configured to electrically connect a power supply circuit configured to output a power supply potential corresponding to an amplitude level of a high-frequency input signal and the first power supply terminal; and a second external power supply line configured to electrically connect the power supply circuit and the second power supply terminal. An inductance value of the first external power supply line is higher than an inductance value of the second external power supply line.

Provided is an amplification circuit that includes: a low-noise amplifier that includes an FET as an amplification element and that amplifies a radio-frequency signal inputted to the gate of the FET; an input matching network that matches the input impedance of the low-noise amplifier; and a switch that is serially connected between ground and a node on a line connecting the input matching network and the gate of the FET to each other.

Provided is an amplification circuit that includes: a low-noise amplifier that includes an FET as an amplification element and that amplifies a radio-frequency signal inputted to the gate of the FET; an input matching network that matches the input impedance of the low-noise amplifier; and a switch that is serially connected between ground and a node on a line connecting the input matching network and the gate of the FET to each other.

An amplifier module includes a module substrate and first and second power transistor dies. The first power transistor die is coupled to a mounting surface of the module substrate, and has first and second input/output (I/O) contact pads and a first ground contact pad, all of which are all exposed at a surface of the first power transistor die that faces toward the mounting surface of the module substrate. The second power transistor die also is coupled to the mounting surface, and has third and fourth I/O contact pads and a second ground contact pad. The third and fourth I/O contact pads are exposed at a surface of the second power transistor die that faces away from the mounting surface of the module substrate, and the second ground contact pad is exposed at a surface of the second power transistor die that faces toward the mounting surface.

An amplifier circuit for a millimeter wave (mmW) communication system includes an amplifier coupled to a matching network, and a variable gain control circuit in the matching network, the variable gain control circuit having an adjustable gain control resistance, the adjustable gain control resistance having adjustable segments and a center node therebetween, the center node coupled to an alternating current (AC) ground.