Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

A power amplifier module includes an output-stage amplifier, a driver-stage amplifier, an input switch, an output switch, an input matching circuit, an inter-stage matching circuit, an output matching circuit, and a control circuit. The input switch selectively connects one of a plurality of input signal paths to an input terminal of the driver-stage amplifier. The output switch selectively connects one of a plurality of output signal paths to an output terminal of the output-stage amplifier. The control circuit controls operations of the driver-stage amplifier and the output-stage amplifier. The input switch, the output switch, and the control circuit are integrated into an IC chip. The control circuit is disposed between the input switch and the output switch.

A power amplifier module includes an output-stage amplifier, a driver-stage amplifier, an input switch, an output switch, an input matching circuit, an inter-stage matching circuit, an output matching circuit, and a control circuit. The input switch selectively connects one of a plurality of input signal paths to an input terminal of the driver-stage amplifier. The output switch selectively connects one of a plurality of output signal paths to an output terminal of the output-stage amplifier. The control circuit controls operations of the driver-stage amplifier and the output-stage amplifier. The input switch, the output switch, and the control circuit are integrated into an IC chip. The control circuit is disposed between the input switch and the output switch.

A monolithic microwave integrate circuit (MMIC) presents as a power amplifier including a 9:1 overlay transformer and artificial low impedance transmission lines. The 9:1 overlay transformer effects the output impedance thereof. The artificial low impedance transmission lines behave as inductors without occupying an amount of space equivalent to that of an inductor having similar properties as the artificial low impedance transmission line.

A monolithic microwave integrate circuit (MMIC) presents as a power amplifier including a 9:1 overlay transformer and artificial low impedance transmission lines. The 9:1 overlay transformer effects the output impedance thereof. The artificial low impedance transmission lines behave as inductors without occupying an amount of space equivalent to that of an inductor having similar properties as the artificial low impedance transmission line.

The present invention includes a first semiconductor chip, a second semiconductor chip, a first inductor, a second inductor, a second capacitor, protective diodes, and a third inductor. A field effect transistor includes a gate terminal, a drain terminal, and a source terminal connected to a ground terminal. The second semiconductor chip includes an input terminal and an output terminal connected in a direct current manner, and includes a first capacitor connected to the input terminal and to the ground terminal. The first inductor is connected between the output terminal and the gate terminal. The second inductor includes a first terminal connected to the input terminal. The second capacitor is connected between a second terminal of the second inductor and the ground terminal. Protective diodes are connected in series in a forward direction, and each has a cathode, and an anode connected to the ground terminal. The third inductor is connected between the cathode and the second terminal.

An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.

An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.

A current reuse type FET amplifier according to the present invention has a capacitance provided between a drain of a first FET in a first stage and a gate of a second FET in a next stage, electrically separates a gate voltage of the second FET from a drain voltage of the first FET, and includes a control circuit controlling the gate voltage of the first FET and the gate voltage of the second FET so that a variation of a drain current of the second FET and a variation of a drain voltage of the first FET are reduced in accordance with a variation of a saturation current Idss of the FET. Furthermore, the current reuse type FET amplifier according to the present invention uses only a depression mode FET to provide a circuit configuration operable with a positive single power source.