A bias circuit for supplying a bias current to an RF power amplifier by using a field-effect transistor (FET) that is controlled by a logic control signal, such as a CMOS logic control signal, for turning on or turning off the bias current supplied to the RF power amplifier, wherein the bias current will be supplied to the RF power amplifier when the FET is on, and the bias current will not be supplied to the RF power amplifier when the FET is off.

A bias circuit for supplying a bias current to an RF power amplifier by using a field-effect transistor (FET) that is controlled by a logic control signal, such as a CMOS logic control signal, for turning on or turning off the bias current supplied to the RF power amplifier, wherein the bias current will be supplied to the RF power amplifier when the FET is on, and the bias current will not be supplied to the RF power amplifier when the FET is off.

Embodiments of the present disclosure provide a digital predistortion processing apparatus, where the apparatus includes an analog-to-digital conversion unit and n digital predistortion elements. The analog-to-digital conversion unit is connected to the n digital predistortion elements. Each digital predistortion element is configured to receive n input signals, perform digital predistortion processing on the n input signals, and then output n processed signals. The analog-to-digital conversion unit is configured to receive the n processed signals, perform signal extraction based on the n processed signals, and output an extracted signal, where a rate of the extracted signal is the same as a rate of each of the n processed signals. For an ultra-large-bandwidth signal, DPD correction may be performed without increasing a technical level of existing components such as an FPGA and an ADC, thereby greatly reducing implementation costs.

Embodiments of the present disclosure provide a digital predistortion processing apparatus, where the apparatus includes an analog-to-digital conversion unit and n digital predistortion elements. The analog-to-digital conversion unit is connected to the n digital predistortion elements. Each digital predistortion element is configured to receive n input signals, perform digital predistortion processing on the n input signals, and then output n processed signals. The analog-to-digital conversion unit is configured to receive the n processed signals, perform signal extraction based on the n processed signals, and output an extracted signal, where a rate of the extracted signal is the same as a rate of each of the n processed signals. For an ultra-large-bandwidth signal, DPD correction may be performed without increasing a technical level of existing components such as an FPGA and an ADC, thereby greatly reducing implementation costs.

A dual-input envelope tracking (ET) integrated circuit (ETIC) and related apparatus are provided. The dual-input ETIC includes an ET voltage circuit configured to generate an ET voltage based on an ET voltage and a first set of parameters. The ET voltage may be provided to a power amplifier circuit(s) for amplifying a radio frequency (RF) signal(s) in an ET power range. The dual-input ETIC also includes a target voltage processing circuit configured to generate the ET target voltage based on a second set of parameters. The dual-input ETIC further includes a control circuit configured to determine the first set of parameters and the second set parameters based at least on the ET power range of the power amplifier circuit(s). As such, it may be possible to optimize the dual-input ETIC performance in a wide-range of modulation bandwidth, thus helping to improve linearity and efficiency of the power amplifier circuit(s).

A dual-input envelope tracking (ET) integrated circuit (ETIC) and related apparatus are provided. The dual-input ETIC includes an ET voltage circuit configured to generate an ET voltage based on an ET voltage and a first set of parameters. The ET voltage may be provided to a power amplifier circuit(s) for amplifying a radio frequency (RF) signal(s) in an ET power range. The dual-input ETIC also includes a target voltage processing circuit configured to generate the ET target voltage based on a second set of parameters. The dual-input ETIC further includes a control circuit configured to determine the first set of parameters and the second set parameters based at least on the ET power range of the power amplifier circuit(s). As such, it may be possible to optimize the dual-input ETIC performance in a wide-range of modulation bandwidth, thus helping to improve linearity and efficiency of the power amplifier circuit(s).

A power amplifier circuit includes a substrate and a semiconductor chip disposed on or above the substrate. The semiconductor chip includes a power amplifier unit that amplifies an RF signal, a ground terminal to which a ground of the power amplifier unit is coupled, and a first circuit element having a first end electrically coupled to the ground terminal without any portion outside the semiconductor chip interposed therebetween, and having a second end. The substrate includes a second circuit element having a first end electrically coupled to an output of the power amplifier unit and a second end electrically coupled to the second end of the first circuit element. The first and second circuit elements constitute a harmonic wave termination circuit. The harmonic wave termination circuit reflects, to the power amplifier unit, a harmonic wave component of the amplified RF signal output from the power amplifier unit.

A power amplifier circuit includes a substrate and a semiconductor chip disposed on or above the substrate. The semiconductor chip includes a power amplifier unit that amplifies an RF signal, a ground terminal to which a ground of the power amplifier unit is coupled, and a first circuit element having a first end electrically coupled to the ground terminal without any portion outside the semiconductor chip interposed therebetween, and having a second end. The substrate includes a second circuit element having a first end electrically coupled to an output of the power amplifier unit and a second end electrically coupled to the second end of the first circuit element. The first and second circuit elements constitute a harmonic wave termination circuit. The harmonic wave termination circuit reflects, to the power amplifier unit, a harmonic wave component of the amplified RF signal output from the power amplifier unit.

A radio-frequency module (10) includes an IC chip (20) and a mounted component (41, 42, 43) mounted on the IC chip (20). The IC chip (20) includes a core substrate (21) composed of a semiconductor having a first main surface (211) and a second main surface (212) opposed to each other, and a metal wiring layer (22) formed on the first main surface (211) of the core substrate (21) and having a contact surface in contact with the first main surface (211) and a third main surface (221) opposed to the contact surface. The mounted component (41, 42, 43) is mounted at the third main surface (221) side.

A radio-frequency module (10) includes an IC chip (20) and a mounted component (41, 42, 43) mounted on the IC chip (20). The IC chip (20) includes a core substrate (21) composed of a semiconductor having a first main surface (211) and a second main surface (212) opposed to each other, and a metal wiring layer (22) formed on the first main surface (211) of the core substrate (21) and having a contact surface in contact with the first main surface (211) and a third main surface (221) opposed to the contact surface. The mounted component (41, 42, 43) is mounted at the third main surface (221) side.