An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor; a second transistor; and a third transistor, wherein: the first, second and third transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. There is also disclosed a receiver incorporating the amplifier and methods of operating the amplifier.

Methods and systems for power amplification of time varying envelope signals are disclosed herein. In one embodiment, a plurality of signals with constant envelope generated from the decomposition of the quantized version of a time varying envelope signal are individually amplified and then summed to form a desired time-varying envelope signal. Amplitude, phase and frequency characteristics of one or more of the constituent signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time varying envelope signal. In another embodiment, a time-varying envelope signal is decomposed into in-phase and quadrature components that are quantized and decomposed into a plurality of quasi constant or constant envelope constituent signals. The constituent signals are amplified, and then summed to construct an amplified version of the original time-varying envelope signal. The signal amplifiers may be Class A, B, AB, C, D, Class F or Class S amplifiers to provide high amplification efficiency.

A bias timing control circuit includes a current source, a bias switch circuit, a duty cycle sensing circuit, and a switching control circuit. The bias switch circuit includes a first path switch, connected between an output node of the current source and a bias amplifying circuit, and a second path switch, connected between the output node of the current source and a temperature compensation circuit. The duty cycle sensing circuit is configured to generate a timing control signal based on a duty cycle of a transmission enable signal. The switching control circuit is configured to control a first turn-on time of the first path switch during an initial startup period, and a second turn-on time of the second path switch during a normal driving period subsequent to the initial startup period to adjust a warm-up time of a power amplifying circuit based on the timing control signal.

A device (100) for driving a self-conducting n-channel output stage field effect transistor (V1) comprising a control signal input (110), a control signal output (120) for connection to a gate electrode (V1G) of the output stage field effect transistor (V1), a first node (N1) connected to the control signal output (120), a second node (N2), and a first transistor (V4). A source electrode (V4S) of the first transistor (V4) is connected to the first node (N1), a gate electrode (V4G) of the first transistor (V4) is connected to the second node (N2) and a drain electrode (V4D) of the first transistor (V4) is either connected to the source electrode of the output field effect transistor (V1) or connected to a supply voltage (+Vdd). A resistor (R1) is connected with one end to the second node (N2). The device (100) is characterized in that the resistor (R1) is connected at the other end to the first node (N1). The first transistor (V4) can be used to cause the supply voltage (Vdd) to be applied to the control signal output when a low-level signal is applied to the control signal input (110).

A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

Embodiments of the disclosure relate to optimizing power efficiency of a power amplifier circuit to reduce power consumption in a remote unit in a wireless distribution system (WDS). A power amplifier circuit is provided in the remote unit to amplify a received input signal associated with a signal channel(s) to generate an output signal at an aggregated peak power. In this regard, a control circuit is configured to analyze at least one physical property related to the signal channel(s) to determine a maximum output power of the power amplifier circuit. Accordingly, the control circuit configures the power amplifier circuit according to the determined maximum output power. By configuring the maximum output power based on the signal channel(s) in the input signal, it may be possible to optimize the power efficiency of the power amplifier circuit, thus helping to reduce the power consumption of the remote unit.

Embodiments of the disclosure relate to optimizing power efficiency of a power amplifier circuit to reduce power consumption in a remote unit in a wireless distribution system (WDS). A power amplifier circuit is provided in the remote unit to amplify a received input signal associated with a signal channel(s) to generate an output signal at an aggregated peak power. In this regard, a control circuit is configured to analyze at least one physical property related to the signal channel(s) to determine a maximum output power of the power amplifier circuit. Accordingly, the control circuit configures the power amplifier circuit according to the determined maximum output power. By configuring the maximum output power based on the signal channel(s) in the input signal, it may be possible to optimize the power efficiency of the power amplifier circuit, thus helping to reduce the power consumption of the remote unit.

A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.

A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.

In accordance with embodiments of the present disclosure, an apparatus may include a signal path comprising a closed-loop analog pulse width modulator having a forward signal path and a feedback path, a variable resistor coupled to an output of the closed-loop analog pulse width modulator, and a control circuit configured to modify the variable resistor in order to modify an output impedance outside of the feedback path of the closed-loop analog pulse width modulator responsive to a condition for switching between a high output impedance mode and a low output impedance mode of the closed-loop analog pulse width modulator or vice versa.