An envelope tracking (ET) current bias circuit includes a rectifying circuit, a phase compensation circuit, and a voltage/current conversion circuit. The rectifying circuit is configured to detect an envelope voltage from a radio frequency (RF) signal. The phase compensation circuit is configured to compensate for a phase of the envelope voltage in which the phase thereof is delayed in the rectifying circuit to output a phase compensated enveloped voltage. The voltage/current conversion circuit is configured to convert the phase compensated envelope voltage into an ET bias current.

Disclosed is a differential voltage supplying apparatus configured to supply, to a neural activity recorder, an input signal generated by combining, with a direct current (DC) power supply, a common-mode signal determined from a voltage applied to a detection electrode and a reference electrode connected to the neural activity recorder, and improve a common-mode rejection ratio of the neural activity recorder and generate a DC power supply.

Disclosed is a differential voltage supplying apparatus configured to supply, to a neural activity recorder, an input signal generated by combining, with a direct current (DC) power supply, a common-mode signal determined from a voltage applied to a detection electrode and a reference electrode connected to the neural activity recorder, and improve a common-mode rejection ratio of the neural activity recorder and generate a DC power supply.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

Methods and devices for a cascode current mirror with low headroom voltage are presented. According to one aspect, a gate voltage to a cascode transistor of an input leg of the current mirror is provided by a feedback block that operates from a mirrored current output by an output leg of the current mirror. The feedback block includes a feedback current mirror that outputs a mirrored current for conduction through a self-biasing diode-connected transistor that generates the gate voltage to the cascode transistor of the input leg. According to yet another aspect, the cascode current mirror includes a start-up circuit coupled between an input to the input leg and a gate of the cascode transistor of the input leg, the start-up circuit generating a start-up voltage during a transition mode of operation of the cascode current mirror. According to one aspect, a transistor is used as the start-up circuit.

A transconductance circuit has an input terminal (V.sub.IN) and an output terminal (Out), a first current source (4) having a gate connected to said input terminal (V.sub.IN); and a second current source (5), in parallel with said first current source, and having a higher transconductance and a wider dynamic range than the first current source. The current sources are configured so that at a low input voltage only the first current source (4) is on. A voltage drop circuit provides a lower bias voltage for the second current source than for the first current source.

A transconductance circuit has an input terminal (V.sub.IN) and an output terminal (Out), a first current source (4) having a gate connected to said input terminal (V.sub.IN); and a second current source (5), in parallel with said first current source, and having a higher transconductance and a wider dynamic range than the first current source. The current sources are configured so that at a low input voltage only the first current source (4) is on. A voltage drop circuit provides a lower bias voltage for the second current source than for the first current source.

A biasing circuit for a capacitive sensor includes a capacitive sensor element configured to produce a sensor voltage at a sense node, and a preamplifier connected to the sense node and configured to amplify the sensor voltage. The biasing circuit has an auxiliary amplifier connected between an output of the preamplifier and the sense node and configured to set a DC component of an input voltage for the preamplifier to a ratiometric DC bias voltage.

A biasing circuit for a capacitive sensor includes a capacitive sensor element configured to produce a sensor voltage at a sense node, and a preamplifier connected to the sense node and configured to amplify the sensor voltage. The biasing circuit has an auxiliary amplifier connected between an output of the preamplifier and the sense node and configured to set a DC component of an input voltage for the preamplifier to a ratiometric DC bias voltage.

A bias circuit includes a replica circuit for an amplifier circuit using a cascode type inverter, and a generation circuit that generates a bias voltage that causes a drain voltage of an input stage transistor of the amplifier circuit to be a saturation drain voltage, based on an output voltage of the replica circuit, and supplies the generated bias voltage to a cascode element of the amplifier circuit and a cascode element of the replica circuit.