An amplifier circuit having low parasitic pole effect includes a preamplifier, an output transistor and a buffer circuit. The buffer circuit generates a driving signal to control the output transistor according to a preamplification signal generated by the preamplifier. The buffer circuit includes: a buffer input transistor generating the driving signal, wherein an input impedance at its control end is less than that of the output transistor; a low output impedance circuit having an output impedance which is less than an inverting output impedance of the buffer input transistor; an amplification transistor generating an amplification signal at its inverting output; and an amplification stage circuit amplifying the amplification signal by an amplification ratio, so that an equivalent output impedance at a non-inverting output of the buffer input transistor is less than or equal to a product of the reciprocal of an intrinsic output impedance thereof and an amplification ratio.

Disclosed herein are power amplification systems that are dynamically biased based on a signal indicative of an envelope of the signal being amplified. The power amplification systems include a power amplifier configured to amplify an input radio-frequency (RF) signal to generate an output RF signal when biased by a biasing signal. The power amplification systems also include a bias component configured to generate the biasing signal based on an envelope signal indicative of an envelope of the input RF signal. The biasing signal can improve or enhance the linearity of the power amplification systems.

Disclosed herein are power amplification systems that are dynamically biased based on a signal indicative of an envelope of the signal being amplified. The power amplification systems include a power amplifier configured to amplify an input radio-frequency (RF) signal to generate an output RF signal when biased by a biasing signal. The power amplification systems also include a bias component configured to generate the biasing signal based on an envelope signal indicative of an envelope of the input RF signal. The biasing signal can improve or enhance the linearity of the power amplification systems.

An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.

An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.

A charge amplifier circuit is provided. The charge amplifier circuit is couplable to a transducer that generates an electrical charge that varies with an external stimulus. The charge amplifier circuit includes an amplification stage having an input node, couplable to the transducer, and an output node. The amplification stage biases the input node at a first direct current (DC) voltage. The charge amplifier circuit includes a feedback circuit, which includes a feedback capacitor, electrically coupled between the input and output nodes of the amplification stage. The feedback circuit includes a resistor electrically coupled to the input node, and a level-shifter circuit, electrically coupled between the resistor and the output node. The level-shifter circuit biases the output node at a second DC voltage and as a function of a difference between the second DC voltage and a reference voltage.

An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.

A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

A bias circuit includes a current mirror circuit, an operational amplifier, and a bias generating circuit. The current mirror circuit includes a reference branch circuit and at least one mirror branch circuit. The reference branch circuit generates a reference current according to a base current, and the at least one mirror branch circuit generates at least one mirrored current according to the reference current. The operational amplifier receives a first voltage from the reference branch circuit and a second voltage from the at least one mirror branch circuit, and adjusts the first voltage by generating a control voltage according to the second voltage. The bias generating circuit is coupled to the at least one mirror branch circuit and generates a bias signal according to the at least one mirrored current.

An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.