Time-to-digital converter (TDC) using multiple Vernier in a cascaded architecture reduces the timing jitter by decreasing the number of the ring oscillator cycles during the measurement processes. Time-to-digital converter (TDC) measurements using a third oscillator for the second Vernier process has significant advantages compared to changing the period of the second oscillator during the measurement cycle. The Vernier architecture described herein may operate with faster oscillators, reducing the number of intervals before converging and leading to a lower time conversion and a better timing jitter Adding multiple cascaded Vernier interpolation may further improve the TDC measurement resolution while having only a small increment of time required to resolve the time interval calculations.

A digital control ring oscillator (DCO) generally comprises a first delay element and at least one second delay element that is coupled to the first delay element, wherein each of the first and second delay elements are disposed laterally with respect to one another in a first direction and include at least one cell. The cell includes a plurality of transistors arranged in at least one stack.

A wireless communication device can include an oscillator circuit. The oscillator circuit can include an oscillator and measurement circuitry coupled to the oscillator. The measurement circuitry can receive an output signal of the oscillator and measure oscillator error by comparing the output signal of the oscillator to a nominal frequency for an amount of time. The oscillator circuit can further include adjustment circuitry to adjust an oscillator frequency of the oscillator based on the measured oscillator error.

A mixed-signal integrated circuit (IC), including: a voltage booster that includes one or more charge pump devices configured to receive an input voltage, an oscillator signal, and a control signal, wherein the one or more charge pump devices comprise a network of capacitors switchable to provide a charged pumped in response to the control signal, and wherein the one or more charge pump devices, using the pumped, generate a boosted voltage based on the input voltage and at least a portion of an amplitude of the oscillator signal, a voltage regulator coupled to the one or more charge pump devices and configured to receive the boosted voltage and generate a regulated boosted voltage based on the boosted voltage, and a control and monitoring engine configured to provide the control signal based on, at least in part, the input voltage, the oscillator signal, and the regulated boosted voltage.

A semiconductor device includes a fin extending from a substrate, a first source/drain feature, a second source/drain feature, and a gate structure on the fin. A distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature.

Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output.

The present disclosure provides an adaptive adjustment circuit in a computer chip having a voltage-controlled oscillator (VCO) and a processor. The adaptive adjustment circuit comprises a frequency difference acquisition module to generate a frequency difference signal based on a first difference between an oscillation frequency of the VCO and a target frequency. The adaptive adjustment circuit also includes a power module to supply a working voltage to the VCO and the processor, adjust the working voltage based on the frequency difference signal, and supply the adjusted working voltage to the VCO and the processor.

A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.

The embodiments described herein describe technologies of a latch-based freerunning oscillator (FRO). The latch-based FROs can be used to generate a random digital value. The entropy of the random digital value is based on the free-running oscillation of the latch-based FRO, as well as the metastability of the latches. The random digital value can be part of an N-bit random number.

A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.