An analog-based architecture is used to produce tap spacings in an n-tap UI-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve UI-spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the UI spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

An example delay circuit is described that includes an input node to receive a first signal, a first circuit path, a second circuit path, an output buffer, and an output node. The first circuit path includes at least one first buffer and a first array of switches. The second circuit path includes at least one second buffer and a second array of switches. The output buffer receives a mixed output of the first circuit path and the second circuit path. The output node transmits a second signal equivalent to the first signal with a programmed delay.

An arithmetic device includes: an arithmetic circuit that includes arithmetic elements connected in series, and sequentially performs multiple repetitions of arithmetic processing, wherein each of the arithmetic elements receives a first time signal and a second time signal, and generates a third time signal and a fourth time signal obtained by delaying the first and second time signals by a time corresponding to a weight coefficient and input data; a converter that converts a difference between the third and fourth time signals output from the arithmetic circuit into an analog signal or a digital signal for every multiple repetition of arithmetic processing; an integrator that integrates analog signals or digital signals converted by the converter; and a comparator that compares the integration result by the integrator with a reference value.

The present utility model relates to an ultra-low voltage two-stage ring voltage-controlled oscillator applied to a chip circuit. The oscillator includes two-stage delay units. The oscillator includes two delay units that are connected end-to-end, and adjusts a working frequency by adjusting delay time of the delay unit. The delay unit includes PMOS transistors M1, M2, M3, and M4, NMOS transistors M5, M6, M7, and M8, and a load capacitor C.sub.L. The two-stage ring voltage-controlled oscillator of the present utility model uses a substrate feed forward bias structure, reduces a threshold voltage of a transistor, reduces a supply voltage, reduces power consumption, has a large tuning range, and is particularly suitable for a system that works at a low supply voltage.

Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.

A control device for a switching voltage regulator having a high-side switch and a low-side switch to supply a switching voltage to a load includes a comparator configured to compare the switching voltage with a reference voltage to provide an enable signal to the low-side switch, and a spike detection circuit configured to receive the switching voltage and output an offset control signal to execute a time shift to the enable signal.

A temperature-compensated ring oscillator circuit includes a plurality of series-coupled inverters in a ring configuration and a plurality of capacitors. Each capacitor couples to an output of a corresponding inverter. A first transistor is included that comprises a first control input and first and second current terminals. The second current terminal couples to the power supply terminal of each inverter. A second transistor is included that comprises a second control input and third and fourth current terminals. A resistor couples to the fourth current terminal of the second transistor at a first node. An amplifier includes a first amplifier input, a second amplifier input, and an amplifier output. The amplifier output couples to the first and second control inputs. The first amplifier input couples to the second current terminal of the first transistor and the second amplifier input couples to the first node.

An integrated circuit includes a plurality of power rail pairs and a circuit chain. Each of the plurality of power rail pairs includes one of a plurality of high power rails configured to provide a first power supply voltage and one of a plurality of low power rails configured to provide a second power supply voltage that is lower than the first power supply voltage. The circuit chain includes a plurality of unit circuits that are cascade-connected such that an output of a previous unit circuit is provided as an input of a next unit circuit. The plurality of unit circuits are connected distributively to the plurality of power rail pairs.

A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.