Time folding power combining circuits convert a continuous wave into a pulsed wave of greater peak power. Such a circuit may comprise: a switch which receives a continuous wave signal as input, and outputs first and second pulsed wave signals along first and second signal paths, respectively, said switch being configured to repeatedly switch connection back and forth between the input and the outputs of the first and second signal paths in a plurality of time frames; a delay line in the second signal path configured to introduce a time delay to the second pulsed wave signal in the second signal path such that the first pulsed wave signal in the first signal path and the time-delayed second pulsed wave signal in the second signal path substantially align in the same time frames; and a combiner, which receives the first pulsed wave signal in the first signal path and the time-delayed pulsed second wave signal in the second signal path as inputs, and combines them into a single combined pulsed wave signal as output.

An imaging device includes an imaging unit, a reference signal generation unit, m (m is an integer of 3 or more) number of column delay units, and a plurality of column AD conversion units. The plurality of column delay units is arranged so as to correspond to two or more and less than m of the column AD conversion units. Each of the plurality of column delay units includes a first delay circuit. The first delay circuit generates a plurality of first delay clocks. The column AD conversion unit includes a comparison unit, a latch unit, and a counter unit. The comparison unit compares a pixel signal with a reference signal, and outputs a control signal corresponding to a comparison result. The latch unit includes a plurality of latch circuits that latches the plurality of first delay clocks on the basis of a state change of the control signal.

A pulse signal generation circuit includes a clock frequency division component, a time delay component and a selection component. The clock frequency division component is configured to perform frequency division on a clock signal to generate a clock frequency division signal; the time delay component is configured to generate a time delay signal based on the clock frequency division signal; and the selection component is configured to receive the clock frequency division signal and the time delay signal at the same time, and select the clock frequency division signal and the time delay signal according to a preset condition to generate a pulse signal.

Embodiments of the present invention provide for a core stage in an application-specific integrated circuit core which drives both a clock pulse signal and a clock pulse negative/complement signal concurrently, thereby resulting in perfectly aligned signals. The core stage can include a pulse generator, a clock distribution circuit, and a set of latches.

An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having a negative gain and a fixed delay may be connected in series with the first delay section. The oscillator circuit may include an output comprising the output of the second delay section having a frequency that is dependent on the delay of the first delay section and the delay of second delay section.

A CMOS all-digital pulse-mixing device includes a plurality of homogeneous logic elements serially connected to form a basic element sequence, an odd-positioned element parallel connection set and an even-positioned element parallel connection set. The basic element sequence includes odd combination positions and even combination positions. The odd-positioned element parallel connection set serially connects with one of the odd combination positions and the even-positioned element parallel connection set serially connects with one of the even combination positions. The odd-positioned element parallel connection set and the even-positioned element parallel connection set are provided to stretch or shrink a pulse mixture, which is distinguished from a conventional full-customized pulse-mixing device.

A memory controller according to an example embodiment of the present disclosure may include a duty ratio adjusting circuit which generates adjusted clock signals in response to a clock signal for strobing data, and a selection circuit which outputs one of the clock signal and the adjusted clock signals to a memory device as an output clock signal. Each of the adjusted clock signals may have a different duty ratio.

A memory controller according to an example embodiment of the present disclosure may include a duty ratio adjusting circuit which generates adjusted clock signals in response to a clock signal for strobing data, and a selection circuit which outputs one of the clock signal and the adjusted clock signals to a memory device as an output clock signal. Each of the adjusted clock signals may have a different duty ratio.

A variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.

A variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.