To provide a signal generation apparatus for use with a ToF camera system that especially adopts the indirect system, which can be ready for various modulation frequencies with a simple configuration.

A signal generation apparatus is provided which includes a first pulse generator configured to generate a pulse to be supplied to a light source that irradiates light to a distance measurement target, a second pulse generator configured to generate a pulse to be supplied to pixels that receive light reflected by the distance measurement target, and a switching section configured to switch a setting of a modulation frequency of the first pulse generator and the second pulse generator within a predetermined period.

An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

The invention relates to a time-delay circuit (1) for a digital signal (3), particularly for a clock signal, comprising:

an input (2) for the digital signal (3);
an oscillator (4) for generating an internal clock signal (5);
at least one delay channel (6) adding a certain delay to the digital input signal (3) based on the internal clock signal (5); and
an output (7) for a delayed digital signal (8).

Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.

Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

A Bluetooth Low-Energy (BLE) transmitter is presented for used in ultra-low-power radios in short range IoT applications. The power consumption of state-of-the-art BLE transmitter has been limited by the relatively power-hungry local oscillator due to the use of LC oscillators for superior phase noise performance. This disclosure addresses this issue by analyzing the phase noise limit of a BLE TX and proposes a ring oscillator-based solution for power and cost savings. The proposed transmitter features: 1) a wideband all-digital phase locked loop (ADPLL) featuring an f.sub.RF/4 RO, with an embedded 5-bit TDC; 2) a 4 frequency edge combiner to generate the 2.4 GHz signal; and 3) a switch-capacitor digital PA optimized for high efficiency at low transmit power levels. These not only help reduce the power consumption and improve phase noise performance, but also enhance the transmitter efficiency for short range applications.

Apparatus and methods for radio frequency (RF) switch control are provided. In certain embodiments, a level shifter for an RF switch includes a first level-shifting n-type transistor, a first cascode n-type transistor in series with the first level-shifting n-type transistor between a negative charge pump voltage and a first output that provides a first switch control signal, a first level-shifting p-type transistor, a first cascode p-type transistor in series with the first level-shifting p-type transistor between a positive charge pump voltage and the first output, and a second cascode p-type transistor between a regulated voltage and a gate of the first level-shifting n-type transistor and controlled by a first switch enable signal.