Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

One example includes a switch system. The system includes a first signal port and a second signal port. The system also includes a first switching path arranged between the first and second signal ports. The first switching path includes at least one first switch and at least one of the at least one first switch being configured as a high-speed switching device. The system further includes a second switching path arranged between the first and second signal ports in parallel with the first switching path. The second switching path includes at least one second switch and at least one of the at least one second switch being configured as a high-performance switching device.

Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.

The present invention introduces an arrangement for enhancing the performance of an electronic circuit comprising a phototransistor (Q). Either a common-collector or a common-emitter connected phototransistor (Q) has a main resistor (R.sub.L), and at least one external bias resistors (R.sub.L2, R.sub.L3, R.sub.L4), each in parallel to one another. The microcontroller may directly control the voltage outputs or act via respective switches (S1, S2) regarding each respective resistor. When the electronic circuit with the phototransistor (Q) is switched on, at least one of the external bias resistors (R.sub.L2, R.sub.L3, R.sub.L4) are switched on. The voltage output rise time is short, and when the bias has been set, the external bias resistor(s) are disconnected functionally. This means that during the actual measurement with the electric circuit, only the main resistor (R.sub.L) is used in the connection.

A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF. Alternatively, the circuit is used as an inverter switch, where at the command to turn ON is supplied, the at least one IGBT is turned ON, followed by the at least one SGTO. When commanded to turn OFF the at least one SGTO is turned OFF followed by the at least one IGBT. This alternative configuration allows the robust, controllable switching speeds of IGBTs and the superior conduction efficiency of SGTOs. The two configurations mentioned above utilize a wide range of SGTO performance, thus the ability to control the SGTOs turn-off speed by reducing its minority carrier lifetime after the device is processed is of large importance. The efficiency of all uses of the circuit can be optimized with the judicious selection of SGTO minority carrier lifetime and the ratio of active area between the SGTO and IGBT devices. In all cases there is a balance between the time the circuit can achieve hard turn-off without current commutation, the conduction efficiency of the circuit and the maximum amount of controllable current. In all cases both the conduction efficiency of the circuit is higher than an IGBT-only based circuit, and the switching performance is higher than a GTO-only based circuit.

A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF. Alternatively, the circuit is used as an inverter switch, where at the command to turn ON is supplied, the at least one IGBT is turned ON, followed by the at least one SGTO. When commanded to turn OFF the at least one SGTO is turned OFF followed by the at least one IGBT. This alternative configuration allows the robust, controllable switching speeds of IGBTs and the superior conduction efficiency of SGTOs. The two configurations mentioned above utilize a wide range of SGTO performance, thus the ability to control the SGTOs turn-off speed by reducing its minority carrier lifetime after the device is processed is of large importance. The efficiency of all uses of the circuit can be optimized with the judicious selection of SGTO minority carrier lifetime and the ratio of active area between the SGTO and IGBT devices. In all cases there is a balance between the time the circuit can achieve hard turn-off without current commutation, the conduction efficiency of the circuit and the maximum amount of controllable current. In all cases both the conduction efficiency of the circuit is higher than an IGBT-only based circuit, and the switching performance is higher than a GTO-only based circuit.

A power electronic module (2) includes at least one semiconductor switch (4) and a gate-source control unit. The gate-source control unit includes an asymmetric transient voltage suppressor (TVS) diode (8) or two Zener diodes (10, 10) or one or more avalanche diodes arranged between the gate terminal (G) and the source terminal (S) of the semiconductor switch (4).

A pre-charge circuit is provided for pre-charging the input node of a capacitive component to which the multiplexer output is fed to a charge level that is close to or approximates the signal output level of the multiplexer when its output is next switched. In order to reduce the level shifting burden on the amplifier in the pre-charge circuit, each pre-charge circuit input channel has a respective capacitor that is able to be switched in and out of series with the respective multiplexer channels, such that the respective capacitors track the signal levels on the multiplexer channels. The provision of the corresponding capacitors for each MUX channel reduces the input current to the pre-charge amplifier, and allows for the level shifting burden to be taken by the capacitors, leading to more stable and lower power operation.

A pre-charge circuit is provided for pre-charging the input node of a capacitive component to which the multiplexer output is fed to a charge level that is close to or approximates the signal output level of the multiplexer when its output is next switched. In order to reduce the level shifting burden on the amplifier in the pre-charge circuit, each pre-charge circuit input channel has a respective capacitor that is able to be switched in and out of series with the respective multiplexer channels, such that the respective capacitors track the signal levels on the multiplexer channels. The provision of the corresponding capacitors for each MUX channel reduces the input current to the pre-charge amplifier, and allows for the level shifting burden to be taken by the capacitors, leading to more stable and lower power operation.

An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switche to the feedback switches to accelerate the pull up or the pull down.