A semiconductor module including a first switching device coupled to a first line, a terminal, at which a first voltage corresponding to a first current flowing through the first switching device is generated, coupled to the first switching device, a second switching device coupled to the first line for allowing a second current corresponding to the first current to flow therethrough, a voltage generation circuit configured to apply, to a second line, a second voltage lower than a power supply voltage, a resistor, across which a third voltage corresponding to the second current is generated, coupled between the second switching device and the terminal, a reference voltage circuit coupled to the terminal for generating a fourth voltage, and a comparator circuit coupled between the first and second lines, for determining whether the first switching device is in an overcurrent state based on a comparison between the third and fourth voltages.

Solid state switching device including: a pair of line terminals including first and second line terminals for electrical connection with a corresponding phase conductor of an electric line; a switching assembly including one or more solid state power switches, the switching assembly having a first and second power terminals electrically connected with the first and second lines terminals, respectively; a heat sink element in thermal coupling with the switching assembly to adsorb heat from the switching assembly; an additional heat extraction arrangement to extract heat from the switching assembly and convey at least a portion of the adsorbed heat along the phase conductor through the first and second line terminals.

An integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin of the IC, each DC blocking module comprising: a capacitor having a first terminal connected to the respective IO pin and a second terminal connected to a node of the circuitry of the IC; and an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor; and a control terminal configured to receive a control signal to switch the ESD protection circuit between: an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and a test mode in which the conduction path is in a conducting state and short circuits the capacitor.

An active gate voltage control circuit for a gate driver of a power semiconductor switching device comprising a power semiconductor transistor, such as a GaN HEMT, provides active gate voltage control comprising current burst mode operation and protection mode operation. The gate-source turn-on voltage V.sub.gs(on) is increased in burst mode operation, to allow for a temporary increase of saturation current. In protection mode operation, a multi-stage turn-off may be implemented, comprising reducing V.sub.gs(on) to implement fast soft turn-off, followed by full turn-off to bring V.sub.gs(on) below threshold voltage, to reduce switching transients such as V.sub.ds spikes. Circuits of example embodiments provide for burst mode operation for enhanced saturation current, to increase robustness of enhancement mode GaN power switching devices, e.g. under overcurrent and short circuit conditions, or to provide active gate voltage control which adjusts dynamically to specific operating conditions or events.

A driver circuit controls a first switch element. A first resistor is connected between the driver circuit and the first switch element. A second switch element is connected to the first switch element. An overcurrent detector circuit controls the second switch element based on an overcurrent current flowing through the first switch element. A second resistor is connected between the overcurrent detector circuit and the second switch element. The first and second resistor is set such that a turn-off time of the first switch element when the second switch element is turned on by the overcurrent detector circuit is longer than a turn-off time of the first switch element when the first switch element is turned off by the driver circuit.

Methods, apparatus, systems and articles of manufacture are disclosed to allow dynamic changing between current limiting methods. A power delivery controller comprising: a power control device; a first current control device, the first current control device to control the power control device when a current level associated with a current flowing between a first device and a second device exceeds a first adjustable current threshold value; a second current control device to control the power control device when the current level exceeds a second adjustable current threshold value; and a configuration manager to, during runtime, set a first configuration setting of the first current control device and a second configuration setting of the second current control device, the first configuration setting and second configuration setting based on a negotiated contract corresponding to the first device and the second device.

A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. One or more non-dissipative elements may be connected between the common node of the first pair of switches and the common node of the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. In one sequence, switches in a selected driver cell may subtract a specified voltage from an input voltage, bypass the selected driver cell, and add the specified voltage to the input voltage.

A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.

A power supply circuit in an embodiment includes a first transistor that supplies an output based on an input power supply voltage to a load or stops the supply of the output to the load, a second transistor, one end of a current path of which is connected to the gate of the first transistor and another end of the current path of which is connected to a reference potential point, the second transistor being turned on and off according to a level of a gate voltage of the second transistor, a capacitor connected between an input end of the power supply voltage and a gate of the second transistor, and a voltage holding circuit connected between the gate of the second transistor and the reference potential point and configured to hold the gate voltage of the second transistor.

One example described herein includes a power switch control system. The system includes a first monitoring terminal coupled to a first terminal of a power transistor and a second monitoring terminal coupled to a second terminal of the power transistor. The power transistor and the power switch control system can form an ideal diode between the first monitoring terminal arranged as an anode and the second monitoring terminal arranged as a cathode. The system further includes a reverse current controller coupled to the first monitoring terminal and the second monitoring terminal and is configured to control activation of the power transistor to conduct a reverse current from the second monitoring terminal to the first monitoring terminal in response to a reverse voltage arranged as a cathode voltage at the second monitoring terminal being greater than an anode voltage at the first monitoring terminal.