Patent classifications
H03K19/00376
Switch with hysteresis
Switch circuitry including an input terminal (1), said input terminal connected to the base of a first transistor (Q1) via a first resistor (R3), said first transistor being an NPN Bipolar Gate Transistor (Q1), said circuitry further comprising a second resistor (R5) connected between the base of said first transistor (Q1) and ground, and including an output line or terminal (3) connected to the collector of said first transistor (Q1), and wherein the emitter of said first transistor (Q1) is connected to ground (earth), said circuitry further including a second transistor (Q2), said second transistor being a PNP Bipolar Gate Transistor, wherein the collector of said second transistor (Q2) is connected via a third resistor (R8) to the base of said first transistor (Q1), and the emitter of said second transistor (Q2) is connected to said input terminal (1), and wherein the emitter of said second transistor (Q2) is additionally connected to the base of said second transistor (Q2) via a fourth resistor (R11); and the base of said second transistor (Q2) being additionally connected to the output terminal (3) via a fifth resistor (R10) and a diode (D1).
SWITCH WITH HYSTERESIS
Switch circuitry including an input terminal (1), said input terminal connected to the base of a first transistor (Q1) via a first resistor R3, said first transistor being an NPN Bipolar Gate Transistor (Q1), further comprising a second resistor (R5) connected between the base of said first transistor Q1 and ground, and including an output line or terminal (3) connected to the collector of said first transistor (Q1), and wherein the emitter of said first transistor (Q1) is connected to ground (earth), said circuitry further including a second transistor (Q2), said second transistor being a PNP Bipolar Gate Transistor, wherein the collector of said second transistor (Q2) is connected via a third resistor (R8) to the base of said first transistor (Q1), and the emitter of said second transistor Q2 is connected to said input terminal (1), and wherein the emitter of said second transistor (Q2) is additionally connected to the base of said second transistor Q2 via a fourth resistor R11; and the base of said second transistor (Q2) being additionally connected to the output terminal (3) via a fifth resistor (R10) and a diode (D1).
Bipolar junction transistor buffer
A buffer circuit includes a first PNP BJT having a first base, a first collector and a first emitter. A first diode has a first cathode and a first anode. The first cathode couples to the first PNP BJT. A second diode has a second cathode and a second anode. The second anode couple to first base, and the second cathode couples to the first emitter. A voltage level shifter circuit coupled to the first anode. The voltage level shifter has a voltage level shifter output. A pre-driver circuit has a pre-driver input coupled to the voltage level shifter output. A second transistor has a second base, a second collector and a second emitter. The second base couples to the output of the pre-driver output. The second collector couples to a negative supply voltage node. The second emitter couples to an output node of the buffer circuit.
BIPOLAR JUNCTION TRANSISTOR BUFFER
A buffer circuit includes a first PNP BJT having a first base, a first collector and a first emitter. A first diode has a first cathode and a first anode. The first cathode couples to the first PNP BJT. A second diode has a second cathode and a second anode. The second anode couple to first base, and the second cathode couples to the first emitter. A voltage level shifter circuit coupled to the first anode. The voltage level shifter has a voltage level shifter output. A pre-driver circuit has a pre-driver input coupled to the voltage level shifter output. A second transistor has a second base, a second collector and a second emitter. The second base couples to the output of the pre-driver output. The second collector couples to a negative supply voltage node. The second emitter couples to an output node of the buffer circuit.