A shift register unit, drive method thereof, gate drive device and display device. The shift register unit includes: an input subcircuit; a reset subcircuit; an output subcircuit configured to provide a clock signal at a clock signal end to a current stage shift register unit output end in response to a voltage signal at the pull-up node and a control signal having a first voltage level, and to disable an output at the current stage output end in response to the control signal having a second voltage level; a pull down control subcircuit configured to provide a second voltage signal having a low voltage level to a pull-down node in response to the voltage signal at the pull-up node, and to provide the voltage signal having a high voltage level to the pull-down node in response to the voltage signal having a high voltage level; and a pull down subcircuit

An apparatus for performing level shift control in an electronic device includes an input stage positioned in a level shifter of the electronic device, and an output stage positioned in the level shifter and coupled to the input stage through a set of intermediate nodes. The input stage is arranged for receiving at least one input signal of the level shifter through at least one input terminal of the input stage and controlling voltage levels of the set of intermediate nodes according to the at least one input signal. The input stage includes a hybrid current control circuit coupled to the at least one input terminal and arranged for performing current control for the input stage. The hybrid current control circuit is equipped with multiple sets of parallel paths for controlling currents passing through the set of intermediate nodes, respectively, each set may include two or more paths in parallel.

Adaptively controlling drive strength of multiplexed power from supply power rails in a power multiplexing system to a powered circuit is disclosed. A power multiplexing circuit in the power multiplexing system includes a plurality of supply selection circuits (e.g., head switches) each coupled between a respective supply power rail and an output power rail coupled to the powered circuit. The power multiplexing circuit is configured to activate a selected supply selection circuit to switch coupling of an associated supply power rail to the output power rail to power the powered circuit. In one example, the supply selection circuits each include a plurality of power switch selection circuits coupled to an associated supply power rail. The power switch selection circuits are configured to be activated and deactivated by a control circuit to adjust drive strength of a multiplexed supply power rail based on operational conditions, which can account for performance variations.

Noise is reduced in a circuit that converts voltage. A voltage conversion circuit includes a conversion transistor, a current source transistor, and a control circuit. In this voltage conversion circuit, the conversion transistor converts a potential of an input signal, the potential being changed from one of two different potentials to the other, by using predetermined current, and outputs the converted signal as an output signal. Furthermore, the current source transistor supplies the predetermined current. Then, in a case where the potential of the input signal is changed to the other potential, the control circuit stops supplying the predetermined current.

A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity, and includes circuitry to compensate for process variations.

In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.

According to an aspect, a current mode logic circuit comprise a first trim resistor and a second trim resistor connected to a supply voltage, a first transistor connected to an input voltage, a second transistor connected to an inverted input voltage and a third transistor and a fourth transistor connected to the first transistor and the second transistor, respectively, in a cascode manner in order to control magnitudes of an output voltage and an inverted output voltage of the current mode logic circuit.

A digital buffer device with self-calibration includes a first buffer circuit, detection circuit, and calibration circuit. The first buffer circuit has a buffer input terminal for receiving an input signal and a buffer output terminal as output of the digital buffer device. The detection circuit includes at least one second buffer circuit for receiving at least one reference signal and generating at least one detection signal to indicate circuit characteristic variations of the at least one second buffer circuit. The at least one second buffer circuit is of a same type of buffer as the first buffer circuit. The calibration circuit has a calibration input terminal for receiving the input signal, and a calibration output terminal coupled to the buffer output terminal. The calibration circuit is for calibrating the first buffer circuit to generate an output signal according to the input signal and the at least one detection signal.

Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

Output signal generation circuitry 100 may be used for converting an input signal 110 from a source voltage domain to an output signal for a destination voltage domain, the destination voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the output signal generation circuitry. The output signal generation circuitry may comprise level shifting circuitry 160 operating from the supply voltage, which is configured to generate at an output node 130 the output signal for the destination voltage domain in dependence on the input signal. The output signal generation circuitry may also comprise tracking circuitry 280A, 280B, 280C, 280D associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component does not exceed the stressing threshold, wherein the tracking circuitry additionally introduces a delay in a change in the output signal in response to a change in the input signal. Timing compensation circuitry 180A, 180B may also be provided, to control the voltage on the output node in a manner to compensate for the delay introduced by the tracking circuitry.