A circuit to isolate a first circuit node from second circuit node at certain times yet connect the first circuit node and second circuit node at other times. For example, the isolation circuit may isolate a reference node from a system ground during certain phases of operation, but temporarily connect the reference node to the system ground during other phases. An isolation circuit of this disclosure may include a pair of MOSFETs in a back-to-back connection. The MOSFETs may be placed between the two nodes to be isolated. The MOSFETS may be driven by a bipolar junction transistor (BJT). A control signal applied to the BJT emitter controls the operation of the pair of MOSFETs. The isolation or connection from the power supply reference node to system ground may be controlled by applying a HIGH or LOW logic signal to the PNP transistor emitter.

A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

The invention relates to a level converter for adjusting a first reference potential and/or a first communication voltage of a first component to a second reference potential and/or a second communication voltage of a second component, wherein the level converter is arranged between the first component and the second component, wherein the level converter has a first transistor with a downstream first resistor, wherein the level converter is configured in such a way that the second reference potential drops at the first resistor in a blocked state of the first transistor and that the second communication voltage drops at the first resistor in an open state of the first transistor.

Embodiments of level shifters are disclosed. In an embodiment, a level shifter includes a transistor connected between an input terminal of the level shifter and an output terminal of the level shifter, a first resistor connected between a first terminal of the transistor and one of the input terminal of the level shifter and the output terminal of the level shifter, a capacitor connected between the input terminal of the level shifter and the output terminal of the level shifter, a current source connected between the output terminal of the level shifter and a fixed voltage, and a resistor divider connected between the first resistor and the output terminal of the level shifter.

In one embodiment, a control circuit may be configured to form a switching signal to switch a power transistor at a frequency to regulate an output voltage of the power supply to a target value wherein the control circuit is configured to operate in a normal operating mode and a start-up mode and wherein the control circuit is configured to switch the switching signal at a target frequency in response to operating in the normal operating mode. A first circuit may be configured to control the frequency of the switching signal to increase from a first frequency to a second frequency that is less than the target frequency in response to operating in the start-up mode.

The present disclosure provides a level shifter including: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal.

Embodiments of level shifters are disclosed. In an embodiment, a level shifter includes a transistor connected between an input terminal of the level shifter and an output terminal of the level shifter, a first resistor connected between a first terminal of the transistor and one of the input terminal of the level shifter and the output terminal of the level shifter, a capacitor connected between the input terminal of the level shifter and the output terminal of the level shifter, a current source connected between the output terminal of the level shifter and a fixed voltage, and a resistor divider connected between the first resistor and the output terminal of the level shifter.

It is to provide a semiconductor device, a semiconductor system, and a method of controlling the semiconductor device capable of reducing the power consumption. According to one embodiment, a semiconductor device includes a photo coupler control circuit that passes the current to a first signal path for a predetermined period when detecting a change of the input signal supplied from the outside, an insulating circuit that transmits a pulse signal indicating the change of the input signal, from the first signal path to a second signal path insulated from the first signal path, according to the current flow to the first signal path, a holding circuit that generates an input reproducing signal as a reproducing signal of the input signal from the pulse signal transmitted to the second signal path by the insulating circuit, and an internal circuit that receives the input reproducing signal generated by the holding circuit.

In one embodiment, a control circuit may be configured to form a switching signal to switch a power transistor at a frequency to regulate an output voltage of the power supply to a target value wherein the control circuit is configured to operate in a normal operating mode and a start-up mode and wherein the control circuit is configured to switch the switching signal at a target frequency in response to operating in the normal operating mode. A first circuit may be configured to control the frequency of the switching signal to increase from a first frequency to a second frequency that is less than the target frequency in response to operating in the start-up mode.

The invention relates to a level converter for adjusting a first reference potential and/or a first communication voltage of a first component to a second reference potential and/or a second communication voltage of a second component, wherein the level converter is arranged between the first component and the second component, wherein the level converter has a first transistor with a downstream first resistor, wherein the level converter is configured in such a way that the second reference potential drops at the first resistor in a blocked state of the first transistor and that the second communication voltage drops at the first resistor in an open state of the first transistor.