The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node nl. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.

Using switches at the inputs surface of the circuit and any conductor we can make any combinatorial logic gates circuit where the inputs and outputs are distinct. Switches do disconnect some 2 pins and connect some 2 pins at a state and do the reverse at the other state. It is possible to have memory by having the outputs back to the inputs if the switches are made with transistor like switches.

A r a level shifter circuit includes a first p-channel kick transistor connected directly across a first cross-coupled p-channel transistor, a second p-channel kick transistor connected directly across a second cross-coupled p-channel transistor, a first gate drive circuit coupled to the gate of the first p-channel kick transistor and configured to turn on first p-channel kick transistor to pull up the first output node in response to a rising edge of a signal at the input node, and a second gate drive circuit coupled to the gate of the second p-channel kick transistor and configured to turn on second p-channel kick transistor to pull up the second output node in response to a falling edge of a signal at the input node.

A touch sensor is provided which includes one or more liquid metal wires and detection circuitry to detect a change in an electrical attribute of the one or more liquid metal cavities based on a depression of the one or more liquid metal cavities, and indicate a touch event corresponding to the depression of the one or more liquid metal cavities based on the change in the electrical attribute.

A battery management system includes a microcontroller having a first diagnostic handler application and first and second applications. The first application sets a first non-recoverable diagnostic flag to a first encoded value having each nibble thereof selected from an odd Karnaugh set of binary values. The second application sets a second non-recoverable diagnostic flag to a second encoded value having each nibble thereof selected from an even Karnaugh set of binary values. The first diagnostic handler application sets a first master non-recoverable diagnostic flag to a first encoded fault value if the first non-recoverable diagnostic flag is equal to a second encoded fault value, or the second non-recoverable diagnostic flag is equal to a third encoded fault value.

A security key associated with a plurality of programmable switches included in an integrated circuit is received. The plurality of programmable switches are set causing the plurality of programmable switches to be conductive. Reset pulses are applied to a first set of programmable switches included in the plurality of programmable switches based on the received security key.