A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

A lookup table circuit constituting a programmable logic device includes: a memory cell array including a plurality of memory cells, each having a resistive memory element; a selection circuit connected to the memory cell array and configured to output, to the memory cell array, a single cell-select signal or two or more cell-select signals for selecting a single memory cell or two or more memory cells among the plurality of memory cells, based on input of a plurality of logic signals; and a read circuit connected to the memory cell array and configured to read data from the single memory cell or the two or more memory cells selected by the single cell-select signal or the two or more cell-select signals, among the plurality of memory cells. The selection circuit is separated from a path along which the read circuit is configured to read data from the memory cell array.

Systems and methods are provided for performing quantum operations. Consistent with disclosed embodiments, a vectorized quantum controller can receive a command from a computing device, the command indicating application of a quantum gate to a qubit of the quantum processor. The vectorized quantum controller can convert the command into one or more quantum assembly instructions, the one or more quantum assembly instructions including a vector instruction for creating a register of qubits, the register including an indication of the qubit. The vectorized quantum controller can execute the one or more quantum assembly instructions to cause the qubit controller to apply the quantum gate to the qubit, and can providing an output to the computing device.

Systems and methods are provided for performing quantum operations. Consistent with disclosed embodiments, a vectorized quantum controller can receive a command from a computing device, the command indicating application of a quantum gate to a qubit of the quantum processor. The vectorized quantum controller can convert the command into one or more quantum assembly instructions, the one or more quantum assembly instructions including a vector instruction for creating a register of qubits, the register including an indication of the qubit. The vectorized quantum controller can execute the one or more quantum assembly instructions to cause the qubit controller to apply the quantum gate to the qubit, and can providing an output to the computing device.

A handheld focused extracorporeal shock wave therapy (f-ESWT) device includes a plurality of piezoelectric elements, a power supply circuit, and a plurality of driver circuits. The piezoelectric elements are each configured to generate an individual shock wave. The power supply circuit is configured to output a first DC voltage and a second DC voltage. The first DC voltage greater than the second DC voltage. The driver circuits are each operably connected to the first DC voltage, the second DC voltage, and to a corresponding piezoelectric element of the plurality of piezoelectric elements. Each driver circuit includes a switching element electronically configurable in an open state and in a closed state. When the switching element is in the open state, the first DC voltage and the second DC voltage are applied to the corresponding piezoelectric element to pre-charge the corresponding piezoelectric element with a DC pre-charge voltage having a first polarity.

A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

The present invention provides the signals received from different antennas (100) in a certain frequency range with micro-miniature input connectors (101) on a printed circuit, amplified and filtered with the help of RF frontend, and then passed to digital domain (109) with analog-digital converter (107) and further then it performs the switching of the signal by transmitting the signal to the FPGA (110). The signal switched in the FPGA (110) is sent to the related digital-analog converter (107) to be routed to the related output port. The digital-analog converter (112), on the other hand, sends the signal analog to one of the micro-miniature output connectors (114) on the output, and performs the reception of the signal from that output port. In the application of the present invention, a structure with a frequency band of 4 MHz - 50 MHz (HF band) and 32 inputs and 32 outputs has been implemented specifically.

The present invention provides the signals received from different antennas (100) in a certain frequency range with micro-miniature input connectors (101) on a printed circuit, amplified and filtered with the help of RF frontend, and then passed to digital domain (109) with analog-digital converter (107) and further then it performs the switching of the signal by transmitting the signal to the FPGA (110). The signal switched in the FPGA (110) is sent to the related digital-analog converter (107) to be routed to the related output port. The digital-analog converter (112), on the other hand, sends the signal analog to one of the micro-miniature output connectors (114) on the output, and performs the reception of the signal from that output port. In the application of the present invention, a structure with a frequency band of 4 MHz - 50 MHz (HF band) and 32 inputs and 32 outputs has been implemented specifically.

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.