Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.

The disclosure relates to an integrated circuit comprising: a first voltage terminal; a second voltage terminal; and a plurality of logic cells, comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells and a spare subset of cells. Electrical connectors are arranged to: connect the gates of the regular subset of cells in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal.

Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.

An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.