A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

The present disclosure pertains to a circuitry for generating random data. The random data can be numbers. The circuitry includes a ring oscillator, a metastable oscillator, a first circuitry, and an analogue circuitry. The ring oscillator has a ring oscillator output frequency selectable through a selectable input of the ring oscillator. The metastable oscillator has a metastable oscillator output frequency selectable through a selectable input of the metastable oscillator. The first circuitry has a ring oscillator chain size selection logic circuit. The analogue circuitry has a capacitor and a switch used for varying frequency of the ring oscillator. The switch is configured to be controlled by the selection logic circuit of the first circuitry.

An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.

A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.

A processing method for applying an analog dynamic circuit to a digital testing tool includes the following steps. In a step (a), a transistor-level analog dynamic circuit is provided. In a step (b), plural equivalent models are designed according to operations of plural transistors in the transistor-level analog dynamic circuit. In a step (c), a substitution operation is performed to substitute the equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit. Consequently, a gate-level substitution circuit is produced. In a step (d), the gate-level substitution circuit is imported into a digital testing tool. Consequently, a test pattern is generated. In a step (e), the transistor-level analog dynamic circuit is tested according to the test pattern.

A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

Multiple polymorphic Multi-Threshold NULL Convention Logic gates that exhibit one function under a higher supply voltage, and the other function under a lower supply voltage and asynchronous polymorphic circuits able to implement two distinctive functionalities controlled by the supply voltage.

High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

According to the present invention there is provided methods and devices for detecting open and/or short circuits in MEMS micro-mirror devices, which use relative comparisons of voltage levels within the MEMS micro-mirror devices for detecting the occurrence of open and/or short circuits.