A stress compensated oscillator circuitry comprises a sensor arrangement for providing a sensor output signal S.sub.Sensor, wherein the sensor output signal S.sub.Sensor is based on an instantaneous stress or strain component a in the semiconductor substrate, a processing arrangement for processing the sensor output signal S.sub.Sensor and providing a control signal S.sub.Control depending on the instantaneous stress or strain component σ in the semiconductor substrate, and an oscillator arrangement for providing an oscillator output signal S.sub.osc having an oscillator frequency f.sub.osc based on the control signal S.sub.Control, wherein the control signal S.sub.Control controls the oscillator output signal S.sub.osc, and wherein the control signal S.sub.Control reduces the influence of the instantaneous stress or strain component σ in the semiconductor substrate onto the oscillator output signal S.sub.osc, so that the oscillator circuitry provides a stress compensated oscillator output signal.

A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Embodiments of the present invention disclose a time-frequency deviation compensation method, and a user terminal. A temperature compensation exception can be identified and a time-frequency deviation caused by the temperature compensation exception can be compensated by implementing the embodiments of the present invention.

A method of compensating for the temperature related frequency drift of an oscillator. The method comprises using an external reference frequency signal to derive oscillator compensation data over a range of operating temperatures, storing the oscillator compensation data in a first table, and, for a given operating temperature, using the first table to obtain corresponding oscillator compensation data and applying that data to provide compensation for the temperature related frequency drift. The method further comprises defining, for the range of operating temperatures, a series of temperature slots each sub-divided into a series of temperature bins. The step of using an external reference frequency signal to derive oscillator compensation data over the range of operating temperatures comprises a) measuring an operating temperature and using the external reference frequency signal to determine oscillator compensation values for respective temperatures as the operating temperature varies; b) accumulating the determined oscillator compensation values in corresponding temperature bins of a second table; c) at spaced intervals in time, using the data accumulated in the temperature bins of the second table to determine or update the oscillator compensation data stored for one or more slots in the first table.

A device and method is presented to allow the high frequency clock generators and functional blocks of a wireless communication device to enter a very low power sleep state while the low frequency reference clock generator within the wireless communications device remains in an active state. The timing block provides methods of increasing and maintaining accuracy of the system timer which may have been reduced by temperature variation or manufacturing defects. The timing block also allows for selection of the highest accuracy clock from among multiple high frequency clock references. A device for timing control is presented comprising at least one high frequency reference clock, a low frequency reference clock and a timing controller for generating a system timer, wherein the timing controller selects one of the at least one high frequency reference clock and processes the low frequency reference clock with the selected high frequency reference clock.

A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

An oscillator includes an oscillation circuit, an operation state signal generation circuit that generates an operation state signal based on an operation state of the oscillation circuit, and a first integrated circuit, the oscillation circuit and the operation state signal generation circuit are disposed outside the first integrated circuit, and the first integrated circuit includes a first digital interface circuit, a D/A conversion circuit that converts a digital signal input via the first digital interface circuit into an analog signal to generate a frequency control signal that controls a frequency of the oscillation circuit, and a terminal to which the operation state signal is input.

A temperature-compensated oscillator includes a resonator element, an oscillating circuit, and a temperature compensation circuit, and a frequency deviation with respect to a frequency at a time point when power supply starts is within a range of ±8 ppb at a time point when 10 seconds elapse from when the power supply starts, within a range of ±10 ppb at a time point when 20 seconds elapse from when the power supply starts, and within a range of ±10 ppb at a time point when 30 seconds elapse from when the power supply starts.

A temperature-compensated oscillator includes a resonator element, an oscillating circuit, and a temperature compensation circuit, and in a case of varying temperature in a temperature range of ±5° C. centered on a reference temperature in intervals of 6 minutes, and assuming observation period as τ, a wander performance fulfills a condition that an MTIE value is equal to or shorter than 6 ns in a range of 0 s<τ≦0.1 s, the MTIE value is equal to or shorter than 27 ns in a range of 0.1 s<τ≦1 s, the MTIE value is equal to or shorter than 250 ns in a range of 1 s<τ≦10 s, the MTIE value is equal to or shorter than 100 ns in a range of 10 s<τ≦1700 s, and the MTIE value is equal to or shorter than 6332 ns in a range of 100 s<τ≦1000 s.

A multi-ladder DAC includes first and second resistor ladders, with a switch-interconnect. The switch-interconnect includes a second set of switches connected between each node of the first ladder and the top and bottom tap points of the second ladder. All other second ladder tap points are part of a loop tied to the nodes above and below each resistor through a second set of switches. Because no current flows through the switches that tie the top and bottom second-ladder tap points to the nodes of the first ladder, avoiding IRswitch error, thereby improving DNL.