An analog-to-digital converter circuit includes: a reference voltage node configured to be supplied with a reference voltage; an analog-to-digital converter circuit unit including a reference voltage input node configured to be electrically connected to the reference voltage node, the reference voltage being input to the reference voltage input node, the analog-to-digital converter circuit unit configured to convert an input analog voltage into a digital value based on the reference voltage; a voltage generation circuit configured to be electrically connected to the reference voltage node and generate an internal operating voltage based on the reference voltage; and a charge compensation circuit configured to operate based on the internal operating voltage, and during operation of the analog-to-digital converter circuit unit, the charge compensation circuit configured to compensate the reference voltage input node for charge.

The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit. The echo calibration circuit makes response coefficients converge according to the error signal and pseudo-noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates codeword offset table according to the offset.

Examples herein relate to electronic devices that include an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that implements timing adjustment based on output statistics. In an example, an electronic device includes an asynchronous SAR ADC, a statistics monitor, and an operation setting circuit. The asynchronous SAR ADC is configured to output output data. The statistics monitor is configured to capture samples at a bit position of the output data. The statistics monitor is further configured to generate an operational setting based on the captured samples. The operation setting circuit is configured to adjust an operating condition of the asynchronous SAR ADC based on the operational setting.

A switched capacitor circuit includes an output capacitor, a first transmission switch, a first reference buffer, a second transmission switch, a second reference buffer and a charge compensation circuit. The output capacitor includes a first terminal and a second terminal, wherein the first terminal is coupled to an output terminal of the switched capacitor circuit, and the second terminal is coupled to a reference node. The first transmission switch is coupled to the reference node. The first reference buffer is coupled to the first transmission switch. The second transmission switch is coupled to the reference node. The second reference buffer is coupled to the second transmission switch. The charge compensation circuit is coupled to the reference node.

An electronic device may include: a power management integrated circuit (PMIC); and a micro controller unit (MCU) electrically connected to the PMIC. The MCU may be configured to: generate, based on a first driving power signal output from the PMIC to drive the MCU, a digital signal for determining an error in a reference signal of an analog-to-digital converter (ADC) included in the MCU; identify an error rate of the digital signal; and determine a mode for controlling a motor driven power steering system, based on the error rate of the digital signal.

A circuit for biasing a transistor is provided. The circuit includes an output terminal configured to be coupled to a gate terminal of the transistor and circuitry. In a first state, the circuitry is configured to output a control signal at a first voltage level for setting the transistor to a first transistor state. In a second state, the circuitry is configured to first output the control signal at a second voltage level different from the first voltage level following by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage level over time.

An analog-to-digital converter according to one or more embodiments is disclosed that converts an analog input to a digital converted value by repeating a conversion data generation operation by a conversion data generator, a potential generation operation by a capacitance DAC, and a comparison operation by a comparator for a resolution bit, the analog-to-digital converter. a comparator operation signal generation circuit predicts the time when a potential generated by the capacitance DAC becomes settled based on a charging or discharging time to a capacitance element whose characteristics are equal to those of the capacitance used in the capacitance DAC, and generates a comparator operation signal to allow the comparator to start the comparison operation.

A reference buffer has many legs each with an upper transistor, a lower transistor, and a resistor or current source as a tail device in series. The source or emitter of the upper (lower) transistor generates an upper (lower) reference voltage. This source follower transistor configuration has a low output impedance and high current. The gate or base of the upper (lower) transistors are driven by a first (second) control node. A control leg has an upper transistor, a lower transistor, and a tail device in series. The source and gate, or emitter and base, are connected together for the upper and lower transistors and generate the upper and lower control nodes. Alternately, the gate or base of the upper (lower) transistor is driven by an op amp receiving an upper (lower) bandgap voltage and the upper (lower) control node as negative feedback.

A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC toa second digital conversion output from the ADC.