A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

Provided is an ADC circuit based signal digitalization method, including: inputting the analog signal to the ADC circuit, and after being converted by the ADC circuit for the first time, outputting a first ADC output value M.sub.i; adjusting the least significant bit of the ADC circuit based on the value of the higher bits of the output value M.sub.i, turning down the least significant bit of the ADC circuit, when all the values of the higher bits of the output value M.sub.i are 0; inputting the analog signal to the ADC circuit again, and then outputting the ADC output value M.sub.i+1 for the i+1 time; outputting the final signal conversion result and the adjusted least significant bit based on all the ADC output values. The present invention could improve the ADC precision of small signals without increasing the ADC circuit size.

Provided are a digital-to-analog conversion circuit and method. The digital-to-analog conversion circuit includes a conversion unit and a first regulating unit. The conversion unit includes a first code value receiving terminal used to receive a first code value, and the conversion unit is used to convert the first code value into an analog signal. The first regulating unit includes a second code value receiving terminal used to receive a second code value. A signal input terminal of the first regulating unit is connected to a signal output terminal of the conversion unit. The first regulating unit is used to acquire a first analog regulation signal according to the second code value, and regulate, by using the first analog regulation signal, an analog signal transmitted by the conversion unit.

A biasing scheme for a voltage-to-time converter (VTC). An example biasing circuit generally includes a reference current source; a feedback loop current source; an amplifier having a first input coupled to a target voltage node, having a second input, and having an output coupled to a control input of the reference current source and to a control input of the feedback loop current source; a first capacitive element; a first switch coupled in parallel with the first capacitive element; a second switch coupled between the feedback loop current source and the first capacitive element; and a third switch coupled between the first capacitive element and the second input of the amplifier.

A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

A time-to-digital converter and a converting method are provided. The time-to-digital converter includes: a phase locked loop unit configured to multiply an input reference clock by using a phase locked loop (PLL); a counting unit configured to count the multiplied input reference clock and record an edge position of an input signal; a delay locked loop unit configured to decompose the multiplied input reference clock into a multi-phase clock using a delay locked loop (DLL), and sense the recorded edge position of the input signal among the decomposed multi-phase clock and record a fine edge position; and a control unit configured to calculate a time difference in time of flight (ToF) between a start signal and a stop signal of the input signal by using the recorded edge position and the recorded fine edge position.

In one embodiment, a waveform generating device includes a first DA converter converting input data, a controller outputting a first signal having a command value based on the input data, and a second signal having a command value differing by a constant value from the first signal, a second DA converter converting the first signal, a third DA converter converting the second signal, and a combiner combining the output of the first DA converter, the output of the second DA converter, and the output of the third DA converter. When a value of a predetermined first high-order bit of the input data is inverted, the controller changes the command value of the first signal such that a value of the first high-order bit or a second high-order bit different from the first high-order bit is inverted.

The A/D converter includes a D/A conversion circuit configured to perform a D/A conversion on a DAC input digital value to output a DAC output signal, a difference output circuit for outputting difference signals based on a difference between the input signal and the DAC output signal, an A/D conversion circuit for performing an A/D conversion on the difference signals to output an ADC output digital value, and a control circuit for outputting the DAC input digital value based on the ADC output digital value. The control circuit outputs a first DAC input digital value and a second DAC input digital value different from the first DAC input digital value, and obtains ADC result data based on a first ADC output digital value obtained in accordance with the first DAC input digital value, a second ADC output digital value obtained in accordance with the second DAC input digital value, and the DAC input digital value.