When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.

An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier.

An interleaved Analog-to-Digital Converter (ADC) has a reference channel receiving an attenuated analog input. The reference channel is also calibrated to remove capacitor-ratio mismatch, static, and dynamic mismatches and produces a linear replica of the data channels with negligible nonlinear errors due to attenuation. Nonlinear errors on the data channels are corrected by Harmonic Distortion HD2 and HD3 coefficients. A counter increments when the sign bit of a nonlinear-corrected channel code is negative. The count is doubled and reduced by a number of samples to generate a HD2 cost function that adjusts the HD2 coefficient in a LMS loop. A HD3 correlation is generated by multiplying the reference channel output by its difference with the nonlinear-corrected channel code. The sign of the correlation code increments a second counter which generates a HD3 cost function whose sign bit adjusts the HD3 coefficient. These 2 counters generate cost functions, eliminating sample storage.

Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2.sup.x where x ranges from 0 to m1 and m is a number of single switched capacitors per input line.

Apparatus and associated methods are disclosed for digital-to-analog conversion with improved performance. In one exemplary embodiment, an apparatus includes a DAC to convert a digital input signal to an analog output signal. The DAC includes a decoder to decode the digital input signal and to provide first and second sets of control signals. The DAC also includes a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals. The DAC further includes an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second set of control signals.

A method of analog to digital conversion for a field device having an analog to digital converter system (ADCS) including an ADC and a plurality of filters. An analog sensing signal is received from a sensor which measures a level of a physical parameter in a manufacturing system that runs a physical process. A level of the physical parameter is compared to reference noise data. Based on the comparing, at least one ADCS parameter is determined. The ADCS parameter is implemented to configure the ADCS. The ADCS is utilized with the ADCS parameter to generate a filtered digitized sensing signal from the analog sensing signal.

A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

According to one embodiment, a semiconductor integrated circuit includes a first converter, a second converter, and an adjustment circuit. The first converter is configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal. The second converter is configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal. The adjustment circuit is configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value.

The present disclosure relates to compensating for temperature variation of a mixer. Embodiments herein may include performing a single-point Fast Fourier Transform (FFT) (or complex downconversion with DC average) for a number of samples to obtain a transform for each of the number of samples, phase aligning a set of phases associated with each transform, and averaging each transform to generate an analog-to-digital converter (ADC) power value. Further, the disclosed embodiments may include generating a compensation value based on the analog-to-digital converter power value and applying the compensation value to the calibration circuit of the mixer to compensate for a second-order intermodulation product.

An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.