Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.

A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register.

An electronic circuit comprises multiple analog-to-digital converter (ADC) circuits and control logic circuitry. The control logic circuitry advances the multiple ADC circuits through multiple time-interleaved conversions that include time-interleaved acquisition phases, conversion phases, and tracking phases. An acquisition phase of a first ADC circuit samples the analog signal, a conversion phase of the first ADC circuit converts the sampled analog signal to a digital value, and the control logic circuitry is configured to update the first ADC circuit with most recent A/D conversion information by a different ADC circuit during a tracking phase of the first ADC circuit before the acquisition phase of the first ADC circuit.

Methods, apparatus, systems and articles of manufacture are disclosed to improve switching conditions in a closed loop system. An example device includes a first switch adapted to be coupled to a first node, a second switch adapted to be coupled to a second node, a capacitor including a first terminal and a second terminal, wherein the first terminal is coupled the first switch, and wherein the second terminal is coupled to the second switch, a first multiplier coupled to the first terminal and to the second terminal, wherein the first multiplier is adapted to be coupled to at least a third node and a fourth node, and a second multiplier coupled to the first terminal and to the second terminal.

Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

Adaptive toggle number compensation techniques for reducing data dependent supply noise in DACs are disclosed. Various embodiments are based on setting a certain target toggle number for a plurality of DAC units used to convert at least a portion of a digital data sample and then applying various adaptive techniques to try to achieve the target toggle number in converting the data sample from digital to analog domain. Adaptive toggle number compensation techniques described herein try to reduce data dependent supply noise by deliberately limiting, to a certain target number, the number of DAC units that undergo a switch from the digital input of 1 to 0 or from 0 to 1 in converting a digital data sample. Compared to the conventional dummy signal generation approach, such adaptive toggle number compensation techniques may provide significant savings in terms of power consumption of a DAC.

A latched comparator comprises a pre-amplifier stage with a positive input (V.sub.in,p), a negative input (V.sub.in,n); and a differential output (V.sub.out) comprising a first output (V.sub.out,1) and a second output (V.sub.out,2), the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor (MN2) and a first cascode transistor (MN4) connected at a first cascode node, the first amplifying transistor (MN2) being controlled by the positive input (V.sub.in,p) and the first cascode transistor (MN4) being connected, opposite to the first cascode node, to the first output (V.sub.out,1); a second cascode pair, comprising a second amplifying transistor (MN3) and a second cascode transistor (MN5) connected at a second cascode node, the second amplifying transistor (MN3) being controlled by the negative input (V.sub.in,n) and the second cascode transistor (MN5) being connected, opposite to the second cascode node, to the second output (V.sub.out,2); a first gain-boosting transistor (MN6) connected between the first output (V.sub.out,1) and the first cascode node; and a second gain-boosting transistor (MN7) connected between the second output (V.sub.out,2) and the second cascode node, wherein the first gain-boosting transistor (MN6) and the second gain-boosting transistor (MN7) are cross-coupled, so that the first gain-boosting transistor (MN6) is controlled by the second output (V.sub.out,2) and the second gain-boosting transistor (MN7) is controlled by the first output (V.sub.out,2).

An analog-to-digital conversion device of the embodiment includes a comparator and a logic circuit including a switch unit and a logic gate unit that receives a signal output from a comparator. The logic gate unit and the switch unit are connected to each other in series between a power supply node and a ground node.

To reduce distortion of output analog signals generated at a current-output DA converter. A DA converter that outputs a differential analog signal corresponding to an input digital signal is provided, including: a current output unit outputting a current corresponding to the digital signal to each of first and second wires; a converting unit outputting, as positive-side and negative-side analog signals, voltage signals based on currents flowing through the first and second wires, respectively; a first noise reducing unit having: a first switch switched to be or not to be electrically connected with the first wire; and a first buffer provided between the first switch and a reference potential; and a second noise reducing unit having: a second switch switched to be or not to be electrically connected with the second wire; and a second buffer provided between the second switch and the reference potential.

A stage, suitable for use in an analog to digital converter or a digital to analog converter where the stage comprises a plurality of slices that can be operated together to form a composite output, can have reduced thermal noise, whilst each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance.