The present disclosure relates to a high-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and an analog-to-digital conversion method. Binary redundancy reassembly is performed to improve a digital-to-analog converter (DAC) capacitor array included in the SAR ADC such that the total number of capacitors included in a capacitor sub-array of the DAC capacitor array is greater than the number of precision bits of the SAR ADC, and the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is greater than the number of precision bits of the SAR ADC is equal to the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is equal to the number of precision bits of the SAR ADC.

A method for improving performance of a superconducting, flux-quantizing analog to digital converter (SFADC), comprising the following steps. The first step involves providing a known digitally-modulated signal as an input to the SFADC. Another step provides for generating an output with the SFADC based on the known digitally-modulated signal. Another step provides for comparing the characteristics of the output with ideal characteristics to identify an individual rapid single flux quantum (RSFQ) element of the SFADC that is contributing one or more of noise and error to the output. Another step provides for altering one or more of a bias, a delay, and a temperature of the individual RSFQ element to reduce one or more of the noise and the error.

An analog-to-digital converter (ADC) system for providing a calibrated voltage measurement without an external reference voltage may include an ADC circuit, including an analog ADC input and a digital ADC output. The ADC system may also include circuitry to generate a first internal reference voltage and a second internal reference voltage. The ADC system may also include circuitry configured to provide a selected output from a number of inputs, wherein the inputs include inputs to receive (1) the first internal reference voltage, (2) the second internal reference voltage, and (3) a user-provided analog signal of interest, wherein the selected output can be connected to the analog ADC input, an external voltage measurement device, or both.

A calibration method of a pipeline analog-to-digital converter (ADC) that includes a residue amplifier includes the following steps: (A) generating an offset voltage; (B) adjusting a first input voltage of the residue amplifier according to the offset voltage and a reference digital code; (C) converting an output voltage of the residue amplifier into a second digital code; (D) performing a correlation operation on the reference digital code and the second digital code to generate an intermediate gain; (E) recording the intermediate gain; (F) repeating step (A) to step (E) to record a plurality of intermediate gains; (G) selecting one of the intermediate gains as a digital gain according to the second digital code; and (H) generating an output digital code according to a first digital code, the reference digital code, the digital gain, and the second digital code.

A digital-to-analog converter (DAC) device includes a DAC circuitry, a calibration circuitry, and a randomization circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to least significant bits of an input signal. The second DAC circuit is configured to output a second signal. The calibration circuitry is configured to compare the first signal with the second signal, in order to calibrate the second DAC circuit. The randomization circuitry is configured to randomize most significant bits of the input signal, in order to generate first control signals, in which the second DAC circuit is further configured to generate the second signal according to the most significant bits or the first control signals.

Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.

Methods and apparatus for calibrating a gain for a circuit block are disclosed. An example method includes receiving a plurality of quantizer offsets, where the plurality of quantizer offsets represent calibration data for a quantizer configured to quantize an output of the circuit block, determining one or more differences based on one or more first quantizer offsets of the plurality of quantizer offsets and on one or more second quantizer offsets of the plurality of quantizer offsets, and determining an incremental change in a gain associated with the circuit block based on the one or more differences.

A method for predictive level-crossing, LC, in an analog-to-digital converter, ADC, is provided. The method comprises the steps of comparing a first input signal sampled during a first sampling period with one of an upper threshold level and a lower threshold level to determine if a level crossing has occurred during said first sampling period. Which one of said two threshold levels that is compared with said first input signal is based on if a level crossing occurred during a prior sampling period directly prior to the first sampling period, and which one of the two threshold levels was compared to a prior input signal sampled during said prior sampling period.

A system and method for compensating segmented DAC intrinsic INL by adjusting the relative strength of DAC thermometer segments. In the method, the strength of each thermometer segment is adjusted sequentially to reduce INL to 0 at one point on each thermometer code range. The strength of the binary section is also adjusted to further reduce INL while conserving output amplitude. The system includes a calibration circuit that senses the DAC differential output and compares it to an ideal output generated from the same DAC via dithering between 0 and a maximum code. The compensation scheme only performs a specific type of DAC compensation, specifically compensating for systematic non-linearity rather than for mismatch-induced non-linearity. The method can also be applied to calibrate a full thermometer DAC.

A composite analog-to-digital converter (ADC) has a low resolution ADC configured to receive and digitize analog data, the low resolution ADC having a low resolution and a high operating speed, one or more high resolution ADCs configured to receive and digitize the analog data, the one or more high resolution ADCs having a resolution higher than the low resolution ADC, and an operating speed lower than the high operating speed of the low resolution ADC, a sample clock generator to provide a sample clock signal to the low resolution ADC and to a clock divider, a mixer to receive the analog data and connected to the one or more high resolution ADCs, a local oscillator connected to the mixer to allow one or more high resolution ADCs to be tuned to sample a portion of a spectrum of the low resolution ADC. A test and measurement instrument contains a composite ADC. A method of operating a composite analog-to-digital converter (ADC), includes receiving an analog signal at a low resolution ADC that operates at a high speed, receiving the analog signal at one or more high resolution ADCs that operate at a resolution higher than the low resolution ADC and at a lower speed than the operating speed of the low resolution ADC, tuning the high resolution ADC to phase align and time align a signal path for the one or more high resolution ADCs to the signal path for the low resolution ADC, producing a spectrum from the low resolution ADC, and producing a portion of the spectrum from the one or more high resolution ADCs.