A calibration method of a pipeline analog-to-digital converter (ADC) that includes a residue amplifier includes the following steps: (A) generating an offset voltage; (B) adjusting a first input voltage of the residue amplifier according to the offset voltage and a reference digital code; (C) converting an output voltage of the residue amplifier into a second digital code; (D) performing a correlation operation on the reference digital code and the second digital code to generate an intermediate gain; (E) recording the intermediate gain; (F) repeating step (A) to step (E) to record a plurality of intermediate gains; (G) selecting one of the intermediate gains as a digital gain according to the second digital code; and (H) generating an output digital code according to a first digital code, the reference digital code, the digital gain, and the second digital code.

A piecewise linear current-mode digital-to-analog converter circuit approximates an exponential output current over a range of input codes by generating linearly varying currents with different slopes of different ranges of the input codes. The piecewise linear current-mode digital-to-analog converter circuit includes a current generator circuit that generates the output current based on a reference voltage and a feedback signal. A variable resistance circuit is used to generate the feedback signal using the output current. Respective values of the reference voltage and the variable resistance circuit vary as a function of the input code.

A method for dynamically calibrating a time-interleaved digital-to-analog converter (DAC) includes receiving a digital input signal, generating, from the digital input signal, an output analog signal using DAC circuitry, generating, from the digital input signal, a model analog signal using DAC modeling circuitry, adjusting a digital model based on the model analog signal and the digital input signal, determining at least one of an offset error and a gain error based on comparing the output analog signal to the model analog signal, and generating an error correction signal based on the at least one of an offset error and a gain error.

A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

A successive approximation ADC includes a switch circuit, a conversion circuit, a comparison circuit and a controller. The conversion circuit outputs first and second comparison voltages that are respectively equal to first and second input voltages when the switch circuit operates in an ON state. The comparison circuit compares the first and second comparison voltages to generate first and second comparison signals. Generation of least significant bits of the first and second comparison signals is related to two first capacitors and two second capacitors of the conversion circuit. When the other bits of the first comparison signal have identical logic values, the controller provides two different voltages respectively to the first capacitors and respectively to the second capacitors; and when otherwise, the controller provides one of the voltages to both of the first capacitors, and provides the other one of the voltages to both of the second capacitors.

There is provided a digital-to-analog converter, DAC. The DAC circuit comprises an input for receiving a digital input comprising a plurality of bits; an LSB transconductance stage; an MSB transconductance stage; a plurality of current sources, the plurality of current sources comprising a first current source and a second current source; and a switching circuit, the switching circuit configurable to modify a coupling between the plurality of current sources and the LSB transconductance stage and the MSB transconductance stage, wherein the switching circuit is configured to: couple the first current source to one of the LSB transconductance stage and the MSB transconductance stage, and couple the second current source to the other of the LSB transconductance stage and the MSB transconductance stage. A third, binary, transconductance stage may also be present.

A delay-domain analog-to-digital converter including a voltage-to-delay circuit and a time-to-digital converter circuit, and a method of calibrating the same. The voltage-to-delay circuit generates a delay signal based on applied calibration voltage, and the delay signal is applied to a first residue stage configured to generate a sign bit and a residue delay signal. The residue delay signal is applied to an input of a successive residue stage, which is configured to generate a sign bit and provide a residue delay signal to inputs of a next successive residue stage. First and second trim circuits are provided in a delay comparator of one of the successive residue stages, and configured to adjust a first response of the residue stage for a calibration voltage in a first range, and to adjust a second response of the residue stage for a calibration voltage in a second range.

In some embodiments, a digital-to-analog converter (DAC) architecture can include an array having a total number of bit cells, and a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells. The selected number can be variable, such that the array consumes a quiescent current that depends on the selected number. The control system can be further configured to change the selected number when a signal condition exceeds a threshold duration.

A cancellation circuit includes a limiter connected to an output of a first transmitter power amplifier that converts in input sinewave to a digital square wave and a digital to time converter (DTC) connected to the limiter. A RF digital to RF converter is connected to the DTC that converts the digital square wave input into an analog RF output. A cancellation amplifier with an input receives an output from the RF digital to RF converter and has an output connected to an output of a second transmitter power amplifier. The cancellation amplifier produces a cancellation signal to cancel an interference signal at the output of the second transmitter power amplifier from the output of the first transmitter power amplifier. A power detector is connected to the output of the second power amplifier that produces a power value detected at the output of the second power amplifier.

A time-interleaved analog to digital converter (ADC) circuit includes an input signal amplitude detector configured to determine an input signal amplitude of an analog input signal, a multi-tone signal generator configured to generate a plurality of analog and digital sinusoidal signals having an amplitude dependent on the determined input signal amplitude, and an analog input summing module configured to provide a summed output analog signal from the analog input signal and the analog sinusoidal signals. A time-interleaved ADC has an input coupled to receive the summed output analog signal from the analog input summing module and configured to provide a timing skew-calibrated digital output signal from the summed output analog signal. A digital output subtractor module is configured to provide a digital output signal at an output of the circuit from the digital output signal from the time-interleaved ADC and the digital sinusoidal signals from the multi-tone signal generator.