A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.

An analog signal generation device according to the present invention includes a DA converter that adjusts a signal level of a digital signal according to a DAC correction amount and then converts the digital signal into an analog signal, a detector that detects the analog signal and outputs a detection signal, a storage unit that stores a characteristic equation for calculating the DAC correction amount, and a control unit, in which in a case where the differential voltage when the digital signal having a signal level of a predetermined value is input to the DA converter is larger than a threshold value, the control unit calculates a new DAC correction amount based on the differential voltage by using the characteristic equation, and in a case where the differential voltage does not fall within the threshold value, the control unit corrects the characteristic equation.

An apparatus as discussed herein can be configured to include a delay line analog-to-digital converter operable to convert an analog error voltage into a digital error voltage signal. Additionally, the apparatus can be configured to include an integrator function as well as a digital to analog converter. The integrator function is operable to produce a digital value representative of an analog input voltage, the digital value adjusted based on samples of the digital error voltage signal generated by the delay line analog-to-digital converter. The digital-to-analog converter operative to convert the digital value received from the integrator function into a second analog voltage, the analog error voltage being a difference between the input voltage and the second analog voltage.

A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.

A method for calibrating a digital-to-analog converter (DAC) can include generating a first output voltage based on a first reference voltage and comparing the first output voltage and a second reference voltage. The method can further include providing an adjustment to the generating based on the comparison of the first output voltage and the second reference voltage, with the adjustment being configured to compensate for a change in the first reference voltage.

A calibration circuit for correcting timing errors introduced by a DAC in a signal path of an ADC, the calibration circuit comprising: an input subtraction module configured to subtract an estimated error from an output of the ADC and provide a corrected output; a filter module configured to approximate an error transfer function corresponding to the DAC timing errors; a correlation module configured to correlate the corrected output with an output from the filter module to extract an error term; an integrator module configured to integrate the error term to provide an updated error coefficient; and a correction module configured to correlate the updated error coefficient with the output from the filter module to provide the estimated error to the input subtraction module.

An electronic circuit comprises multiple analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A/D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A/D conversions.

A digital-to-analog converter (DAC) calibration system for calibrating N DAC cells in a DAC, where N can be an integer number of DAC cells greater than 2, can include a processor, which can be configured to configure the DAC to generate N reference outputs, configure the DAC to generate N calibration outputs, and determine N overall error values corresponding to a difference between respective individual ones of the N calibration outputs and the N reference outputs. The processor can also be configured to determine, such as using the N overall error values, a cell error value for each of the N DAC cells.

An A/D converter includes: a first reference voltage unit that generates a temperature-compensated reference voltage; a second reference voltage unit that generates a second reference voltage calibrated with the reference voltage; an integration unit that generates an integrated voltage obtained by integrating unit voltages using any one of the reference voltage, the second reference voltage, and a ground voltage as an initial value during calibration; a comparator that compares the integrated voltage with a threshold voltage and outputs a determination signal; a calibration control unit that measures an integration time until the integrated voltage exceeds the threshold voltage from the initial value during calibration and calibrates the unit voltages and an offset voltage of the comparator; and a conversion control unit that converts an input voltage into a digital value using a conversion integration time which is the integration time when the input voltage is an initial value and the second reference voltage during conversion.

An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.