Certain aspects of the present disclosure provide techniques and apparatus for digital-to-analog conversion. An example apparatus generally includes a digital-to-analog converter (DAC), an incremental analog-to-digital converter (IADC) having a first input coupled to a first output of the DAC, and a controller coupled to the DAC and the IADC. The controller is configured to determine a direct current (DC) offset associated with the DAC using the IADC and control a mission-mode digital input signal of the DAC based on the DC offset.

Signal processing systems with mitigation of interference of between alike calibrations are disclosed. In certain embodiments, a signal processing system includes a shared signal processing channel that processes an input signal to generate an output signal, and two or more signal processing slices that each process the output signal from the shared signal processing channel. The shared signal processing channel has an error of a first type, and the signal processing slices each have an error of the first type. The signal processing system further includes a calibration system that provides the signal processing slices with slice correction coefficients that compensate the signal processing slices for the slice errors. The calibration system adjusts each of the slice correction coefficients based on an estimate of the error of the shared signal processing channel.

An example transmitter includes: an output comprising a first terminal and a second terminal; a driver having first transistor switches coupled to first current sources; a first circuit having a first transistor coupled between the first transistor switches and the first terminal, and a second transistor coupled between the first transistor switches and the second terminal; and a second circuit, coupled between the output and gates of the first and second transistors, configured to bias the first transistor with a first fraction of a first voltage signal at the first terminal and bias the second transistor with a first fraction of a second voltage signal at the second terminal.

A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

A system includes a primary analog-to-digital converter (ADC) having an input electrically coupled to an input voltage, the primary ADC configured to sample the input voltage at a frequency and convert sampled input voltages to respective primary ADC digital outputs; and a trained calibration engine having an input electrically coupled to an output of the primary ADC, the trained calibration engine including a trained machine-learning (ML) model configured to correct each primary ADC digital output to a respective corrected digital output, the trained ML model having been trained with reference digital outputs from a reference ADC and training digital outputs from the primary ADC, the reference digital outputs representing ground-truth data for modeling the training digital outputs from the primary ADC.

The systems and methods discussed herein related to analog to digital conversion. An apparatus can include an analog to digital converter including a loop circuit and a comparator circuit. The apparatus can also include a first circuit configured to provide comparator offset calibration for the comparator circuit and a second circuit configured to provide loop calibration for the loop circuit.

In one example, a circuit comprises: a current source having a current output; a switch coupled between the current output and a current terminal, the switch having a switch control input; a pulse signal generator having pulse signal outputs, the pulse signal generator configured to provide pulse signals having different pulse widths at the pulse signal outputs; and a multiplexor circuit having pulse signal inputs, a selection input and a selected pulse signal output, the selected pulse signal output coupled to the switch control input, and the pulse signal inputs coupled to the pulse signal outputs.

Novel solutions for calibration of a digital-to-analog converter (DAC). Some solutions allow for the calibration of a DAC without an isolation switch and/or calibration based on signal measurements taken at the output stage of a device comprising the DAC.

In an ADC calibration device, the calibration signal generator generates a frequency modulated wave, as a calibration signal, in which frequency changes in a frequency pattern, which is predetermined, within an applicable frequency range over time. A TI-ADC outputs a sample signal obtained by performing an AD conversion of the calibration signal input. Individual frequency characteristic detection units are provided in parallel corresponding to the plurality of AD converters and individually detect frequency characteristics of the sample signal for each of the plurality of AD converters. In a control unit, a mismatch calculation unit calculates frequency characteristics of mismatch characteristics between the plurality of AD converters from the frequency characteristics of the sample signal for each of the plurality of AD converters, and calculates correction information for correcting a mismatch.

A digital-to-analog converter (DAC) can include an array having a total number of bit cells, and a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells. The selected number can be variable, such that the array consumes a quiescent current that depends on the selected number. The control system can be further configured to change the selected number when a signal condition exceeds a threshold duration.