The present disclosure relates to a digital-to-analog converter comprising an impedance network and a transfer function modification circuit. The transfer function modification circuit comprises a DAC and a demultiplexer. The demultiplexer may be used to selectively connect the output of the DAC to different respective nodes of the impedance network, allowing positive or negative currents to be injected into the node and modify the transfer function. By using a demultiplexer to selectively couple to different nodes, the node into which the current is injected may be modified post-manufacture, allowing transfer function modification.

An AD converter device includes: a plurality of AD converter circuit units which performs analog-to-digital conversion in a time-interleaved manner; and a multiplexer circuit which generates a digital signal from output signals of the AD converter circuit units. The multiplexer circuit includes logic circuits and intermediate connection wirings placed to be distributed in the AD converter circuit units, the logic circuits are connected in a tournament configuration. In each of the AD converter circuit units, an output circuit and a first element circuit part including the logic circuit are placed along a first outer periphery and the intermediate connection wirings are placed to cross in a first direction. The AD converter circuit units are placed along the first direction with two adjacent ones of the AD converter circuit units set as a pair and with the output circuits and the first element circuit parts facing each other for each pair.

An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

An example receiver includes a comparator configured to compare an analog signal and a reference signal; an analog-to-digital converter (ADC) having an input configured to receive the analog signal and an output configured to supply a digital signal; a first circuit configured to supply the analog signal to the input of the ADC, the first circuit configured to apply, under control by output of the comparator, a first operation to the analog signal; and a second circuit configured to receive the digital signal from the output of the ADC, the second circuit configured to apply, under control of the output of the comparator, a second operation to the digital signal. In some examples, the analog signal can be an orthogonal frequency division multiplexing (OFDM) signal.

An analog-to-digital converter (ADC) includes: a time-domain ADC core; and a calibration circuit. The time-domain ADC core includes: a first delay-to-digital stage having a terminal; a second delay-to-digital stage having a terminal; a third delay-to-digital stage having a terminal. The calibration circuitry is coupled to the terminal of the first delay-to-digital stage, the terminal of the second delay-to-digital stage, and the terminal of the third delay-to-digital stage of stages. The calibration circuitry is configured to calibrate the first delay-to-digital stage, the second delay-to-digital stage, and the third delay-to-digital stage based on a zero-crossing calibration and an over-range calibration. The over-range calibration sets a maximum threshold and a minimum threshold for the time-domain ADC relative to a reference voltage.

Disclosed is a circuit including timer interleaved (TI) analog-to-digital converter (ADC) circuitry which generates digital output signals. Correction circuitry receives the digital output signals from the TI ADC circuitry and generates corrected output signals using weight values to correct time skew. The correction circuitry includes a derivative filter which removes frequency dependency between the weight values and input signals to the TI ADC circuitry. Weight updating circuitry receives the corrected output signals and generates updated weight values for the correction circuitry. The weight updating circuitry includes a notch filter which suppresses spectral content in the corrected output signals to cancel spurious correlations in the weight updating process.

A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

A complementary metal-oxide-semiconductor (CMOS) temperature sensor with wide-range sensing capability and high energy-efficiency is provided by a device, having: a bipolar junction transistor (BJT) core; an Analog to Digital Converter (ADC); a digital controller; and an amplifier configured to receive a selection signal from the digital controller to provide a voltage differential from the BJT core to the ADC at one of a first gain or a second gain, different from the first gain based on a temperature sensed by the BJT core. Additionally, a method of operation thereof is provided that includes: calibrating first and second gains associated with respective first and second temperature ranges for a temperature sensor at a shared temperature; determining whether a reading temperature for the temperature sensor is within the first or second temperature range; and applying one gain based on which temperature range the reading temperature is within.

A current digital-to-analog converter may be used in a system for measuring temperature of a thermistor, with mismatch reduction techniques applied to digital-to-analog converter elements of the digital-to-analog converter in order to maximize accuracy and precisions of the temperature measurement.

Disclosed herein is a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a capacitive digital-to-analog converter (DAC) including a binary-weighted capacitor array, and a bridge capacitor separating the binary-weighted capacitor array into a first switched capacitor array connected to a first node and a second switched capacitor array connected to a second node, with a first terminal of the bridge capacitor being connected to the first node and a second terminal of the bridge capacitor being connected to the second node. A multipurpose capacitor is connected to the first node, with the multipurpose capacitor serving as both a termination capacitor for the first switched capacitor array and a shield between the first node and the bridge capacitor. A dummy is capacitor connected to the second node and serving as a shield between the second node and the bridge capacitor.