A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M1 sampling phases of the M sampling phases. The phase control circuit comprises M1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.

A signal adjustor receives a first signal such as feedback associated with generation of an output voltage. The output voltage is regulated based on a selected setpoint reference voltage. The signal adjustor maps a magnitude of the selected setpoint reference voltage to a first set of signal adjustment information amongst multiple sets of signal adjustment information. The signal adjustor then applies the first signal adjustment information to the first signal to produce a second signal.

An AD converter with self-calibration function that does not require an instrument for calibration, and includes: a reference voltage unit that generates a reference voltage; a summation and conversion unit that has two or more unit voltages serving as units of amount of change in a summed voltage, and during conversion, sums up any one unit voltage of the two or more unit voltages until the summed voltage exceeds the reference voltage, with an input voltage being an initial value of the summed voltage; and a control unit including a calibration control section that calibrates the two or more unit voltages and an offset voltage of a comparator at a time of calibration, and a conversion control section that determines a polarity of the offset voltage of the comparator and thereafter converts the input voltage to a digital value during conversion.

Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.

We disclose an apparatus for determining one or more calibration values of an ADC, the apparatus configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal comprising the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal comprising the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal, the apparatus configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.

Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a set of filtering components configured to at least filter image components and cause a phase shift in the output signals. One or more delay adjustment components can cause a delay to at least the output of the parallel ADCs and the set of filtering components. A cross-correlating component can be utilized to cross-correlate the output of the parallel ADCs with an output signal of at least one filtering component of the set of filtering components and an output signal of at least one delay adjustment component of the set of delay adjustment components. A conversion component determines polar coordinates from rectangular coordinates from the output of the cross-correlating component. Thereafter, a time-offset and gain estimator component can determine one of gain error calibration data or time-offset calibration data based at least in part on an output signal of the conversion component, which can be stored and/or used to calibrate individual time-interleaved ADCs.

A time-interleaved analogue-to-digital converter including a first analogue-to-digital converter and a second analogue-to-digital converter, each arranged to sample a respective analogue input periodically and produce a respective digital output based on the sampled analogue input, and also including a signal interleaving portion, arranged to combine the digital outputs to produce a digital output signal. The time-interleaved analogue-to-digital converter is configured for operation both in an operational mode and a calibration mode. In the operational mode, the second analogue-to-digital converter is arranged to sample the analogue input a first time period after the first analogue-to-digital converter samples the analogue input. In the calibration mode, the second analogue-to-digital converter is arranged to sample the analogue input simultaneously with the first analogue-to-digital converter, or a second time period apart from a time at which the first analogue-to-digital converter samples the analogue input. The second time period is shorter than the first time period.

A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

A semiconductor device, a signal processing system, and a signal processing method are provided that regulate a change of characteristics in the event of aged deterioration. The semiconductor device of the present invention includes a reference voltage generation circuit that generates a reference voltage, an analog signal processing circuit that outputs a first processing signal according to the reference voltage, a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal, an input section that receives a regulation signal for the outputted test signal, and a regulator circuit that regulates the output of the analog signal processing circuit in response to the regulation signal.