A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

Offset calibration for an analog front-end system is provided. The analog front-end system includes a variable-gain amplifier, and the calibration mitigates an offset error of the variable-gain amplifier. Calibration is based on a difference-based estimation technique combined with digital iteration. Difference-based estimation includes measuring different digital output signals from an analog-to-digital converter for different respective gains of the variable-gain amplifier. The digital iteration is utilized to estimate offsets values which converge a digital output difference to a target of zero volts.

Random chopping is an effective technique for data converters. Random chopping can calibrate offset errors, calibrate offset mismatch in interleaved ADCs, and dither even order harmonics. However, the non-idealities of the (analog) chopper circuit can limit its effectiveness. If left uncorrected, these non-idealities cause severe degradation in the noise floor that defeats the purpose of chopping, and the non-idealities may be substantially worse than the non-idealities that chopping is meant to fix. To address the non-idealities of the random chopper, calibration techniques can be applied, using correlators and calibrations that may already be present for the data converter. Therefore, the cost and digital overhead are negligible. Calibrating the chopper circuit can make the chopping more effective, while relaxing the design constraints imposed on the analog circuitry.

The invention relates to a circuit arrangement comprising a control device, an input circuit for applying an input signal, a conditioning circuit electrically connected to the input circuit for converting the input signal into a measured signal, an analog-to-digital converter electrically connected to the conditioning circuit for converting the measured signal into a digital value, and a reference source that outputs a known reference signal. In this respect, a first switching apparatus is provided that selectively separate the input signal from the conditioning circuit or supplies it to the conditioning circuit and a second switching apparatus is provided that selectively supplies the reference signal to the input circuit or separates it from the input circuit, wherein the control device is configured to determine an offset error and to determine a gain error of the circuit arrangement.

Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a gradient-based optimization approach or other such optimization approach to determine optimized gain error calibration data to compensate for gain mismatch in and between individual parallel time-interleaved ADCs and to determine time-offset calibration data to compensate for timing errors in and between individual parallel time-interleaved ADCs. For example, once a calibration signal is applied to an ADC, the output of the ADC can be analyzed to determine a spectrum of the calibration signal. One or more images (e.g., phasors) of the spectrum can be determined and used to determine initial values of the optimization. Thereafter, the optimization approach can be utilized to determine optimized gain error calibration data and optimized time-offset calibration data, which can be stored and/or used to calibrate individual time-interleaved ADCs.

An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M1 sampling phases of the M sampling phases. The phase control circuit comprises M1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.

An apparatus is provided which comprises: a thermal sensor comprising one or more n-type devices or p-type devices that suffer from subthreshold factor variation, wherein the thermal sensor is to generate an output digital code representing a temperature; and a calibration circuitry coupled to the thermal sensor, wherein the calibration circuitry is to trim the effects of subthreshold factor variation from the output digital code.

Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.

The digital temperature sensing circuit includes a temperature voltage generator configured to generate a temperature voltage varying with a temperature in response to a first reference voltage, divide a supply voltage in response to a second reference voltage, and generate a high voltage and a low voltage, a code voltage generator configured to divide the second reference voltage based on the high voltage and the low voltage and output divided voltages having different voltage levels, and a mode selector supplied with the temperature voltage and the divided voltages, and configured to output a first code or a second code in response to a mode select signal, wherein the first code and the second code have different numbers of bits.