An analog-digital conversion apparatus includes: an analog-digital converter (ADC) included in an integrated circuit (IC) and configured to operate based on a sampling clock constituting a portion of a plurality of clocks; and a driver included in the IC and configured to operate based on another portion of the plurality of clocks, and produce a driving signal based on a digital value output from the ADC. The ADC and the driver are synchronized with each other based on an interrupt request (Irq) of the IC.

In one embodiment, a waveform generating device includes a first DA converter converting input data, a controller outputting a first signal having a command value based on the input data, and a second signal having a command value differing by a constant value from the first signal, a second DA converter converting the first signal, a third DA converter converting the second signal, and a combiner combining the output of the first DA converter, the output of the second DA converter, and the output of the third DA converter. When a value of a predetermined first high-order bit of the input data is inverted, the controller changes the command value of the first signal such that a value of the first high-order bit or a second high-order bit different from the first high-order bit is inverted.

According to the one embodiment, a semiconductor circuit includes: an analog-to-digital conversion circuit including a first analog-to-digital converter configured to sample at least one first sampling signal regarding an input signal based on a first clock, and a second analog-to-digital converter configured to sample at least one second sampling signal regarding the input signal based on a second clock shifted from the first clock by a first time; and a first calibration circuit configured to calibrate at least one timing of the first clock and the second clock based on a calculation result of a moving average of the first sampling signal and the second sampling signal.

A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.

A measurement system includes a source unit to provide a source signal to a sample and a voltage source and/or a current source and a memory. The system also includes a measurement unit configured to acquire from the sample an measurement signal that may be responsive to the source signal and a voltage measuring unit, a current measuring unit, and/or a capacitance measuring unit, and a memory. The system also includes a control unit including a digital signal processing unit; a source converter; a measurement converter. The system further includes a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, the measurement converter, the source unit, and the measurement unit; a calibration unit for calibrating aspects of the system including the control unit; and a reference voltage supply configured to supply a common reference voltage for the control unit.

An analog signal generating source comprising two or more digital-to-analog converters (DAC) combined to generate one or more frequency components. The analog signal source comprises a first path for generating substantially low frequency signals, the first path comprising a first one of the DACs; and a second path for generating substantially high frequency signals, the second path comprising a second one of the DACs. The analog signal source also comprises a data processor for processing an input signal and providing the processed input signal to the first and second paths; a combining circuit configured to combine outputs of the first and second paths into the source signal; a feedback portion configured to sense the source signal; and a servo loop configured to use the sensed source signal to adjust as need to maintain the source signal to substantially agree with the input signal.

A measurement system includes a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and a plurality of analog-to-digital converter (ADC) outputs from a plurality of ADCs, wherein each ADC output has a path, and a gain of each output path is made up of a plurality of gain stages in the gain chain; and a mixer configured to combine the plurality of ADC outputs into a single mixed output.

An image sensor includes a pixel array having a plurality pixels arranged in a plurality of pixel clusters coupled to a plurality of column busses, a plurality of voltage supplies coupled to the plurality of pixel clusters, and ping-pong readout circuitry. Pixel clusters in adjacent column busses are supplied with different voltage supplies. The ping-pong readout circuitry includes multiplexing circuitry coupled to the plurality of column busses, and a plurality of analog-to-digital converters coupled to the multiplexing circuitry. The image sensor also includes a controller configured to selectively couple a pixel signal of a pixel cluster to a column bus to an ADC for signal conversion.

A digital slope analog to digital converter device includes a capacitor array circuit, a switching circuitry, comparator circuits, encoder circuitries, and a control logic circuit. The capacitor array circuit generates a first signal according to an input signal and switching signals. The switching circuitry generates the switching signals according to an enable signal and a first valid signal in the valid signals. Each of the comparator circuits compares the first signal with a predetermined voltage, in order to generate a corresponding one of the valid signals. Each of the encoder circuitries receives the switching signals according to a corresponding one of the valid signals, in order to generate a corresponding one of sets of first digital codes. The control logic circuit performs a statistics calculation according to the sets of first digital codes, in order to generate a second digital code.

A digital slope analog to digital converter device includes a capacitor array circuit, a switching circuitry, comparator circuits, encoder circuitries, and a control logic circuit. The capacitor array circuit generates a first signal according to an input signal and switching signals. The switching circuitry generates the switching signals according to an enable signal and a first valid signal in the valid signals. Each of the comparator circuits compares the first signal with a predetermined voltage, in order to generate a corresponding one of the valid signals. Each of the encoder circuitries receives the switching signals according to a corresponding one of the valid signals, in order to generate a corresponding one of sets of first digital codes. The control logic circuit performs a statistics calculation according to the sets of first digital codes, in order to generate a second digital code.