A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.

A wide-band analog input signal is converted into a digital output signal on the basis of a band division method without the need for filter circuits. An analog processing block A.sub.j (j=2 to N, where N is an integer) down-converts an analog input signal S.sub.x using a cutoff frequency fj-1 of a channel CH.sub.j-1 and A/D-converts an analog signal S.sub.aj acquired as a result. A digital processing block B.sub.j doubles the signal strength of a first digital signal S.sub.1j acquired by A.sub.j, subtracts a third digital signal S.sub.3j-1 of the channel CH.sub.j-1 from a second digital signal S.sub.2j acquired as a result, up-converts the acquired third digital signal S.sub.3j using the cutoff frequency f.sub.j-1, and outputs the result to an adder as a channel output signal S.sub.yj of a corresponding channel CH.sub.j.

A circuit arrangement includes a microcontroller having a first analog-to-digital converter whose input is connected to the output of a first multiplexer whose output is connected to a first comparison device for comparing reference voltages, and a first serial interface circuit connected to the first comparison device. A voltage generating circuit includes a second analog-to-digital converter whose input is connected to the output of a second multiplexer whose output is connected to a number of registers, which are connected to a safety value generator and store digital values together with a respective safety value, and a second serial interface circuit connected to the registers. The first and second serial interface circuits are connected to each other for communication of the microcontroller with the voltage generating circuit, the first interface circuit being connected to a second comparison device for comparing supply voltages and/or currents with desired voltages and/or desired currents.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines calculating signals, to which the second quantized outputs correspond in a predetermined interval, and averages the calculating signals to generate a reference signal, and compares the reference signal with each of the calculating signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits are configured to convert an input signal according to interleaved clock signals to generate first quantized outputs. The calibration circuit is configured to perform at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit further includes a first adjusting circuit. The first adjusting circuit is configured to analyze adjacent clock signals according to part of the second quantized outputs to generate adjusting information. The skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs and the adjusting information to generate adjustment signals. The adjustment signals are configured to reduce clock skews of the ADC circuits.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines calculating signals, to which the second quantized outputs correspond in a predetermined interval, and averages the calculating signals to generate a reference signal, and compares the reference signal with each of the calculating signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.

The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.

A test and measurement instrument includes a coefficient storage facility coupled to a programmable filter. The coefficient storage facility is configured to store at least two pre-determined filter coefficient sets, and configured to pass a selected one of the at least two pre-determined filter coefficient sets to the filter based on a measurement derived using a compensation oscillator. The measurement may include clock delay and clock skew. In some examples the test and measurement instrument may additionally adjust clock delay and/or clock skew in addition to selecting appropriate filter coefficients.

According to one embodiment, a sensor device includes a switch, a control circuit and an A/D converter. The switch is connected to a sensor element configured to store charge and provided to read the charge stored in the sensor element from the sensor element. The control circuit is configured to control the switch so as to partially and sequentially read the charge stored in the sensor element. The A/D converter is connected to the switch, which is configured to output a digital signal obtained by A/D-converting an analog signal according to the charge, for each charge partially read via the switch.

A photonically-sampled electronically-quantized analog-to-digital converter generates an optical signal comprising a series of optical pulses. The optical signal is split into a first and a second optical path. The split optical signal is detected in the first path and then the detected optical signal is converted to a reference digital signal. The split optical signal in the second path is modulated with an input RF signal and a plurality of demultiplexed RF-modulated optically-sampled signals is generated from the modulated optical signal. The plurality of demultiplexed RF-modulated optically-sampled signals is then pulse broadened, detected, and converted to a plurality of sampled-RF digital signals. The reference digital signal and the plurality of sampled-RF digital signals are digital signal processed to generate a digital representation of the input RF signal.