An A/D converter and an image sensor are disclosed. The image sensor includes: a pixel array including a plurality of pixels; a ramp signal generator configured to generate a ramp signal; and a comparison circuit configured to output a comparison result signal by comparing a pixel signal output by the pixel array with the ramp signal. The comparison circuit includes: a first comparator stage configured to output a first stage output signal according to a result of comparing the pixel signal with the ramp signal, to a first circuit node; a limiter including an n-type transistor having one end connected to the first circuit node and an opposite end to which power supply voltage is applied; and a second comparator stage configured to generate the comparison result signal by shaping the first stage output signal.

An A/D converter and an image sensor are disclosed. The image sensor includes: a pixel array including a plurality of pixels; a ramp signal generator configured to generate a ramp signal; and a comparison circuit configured to output a comparison result signal by comparing a pixel signal output by the pixel array with the ramp signal. The comparison circuit includes: a first comparator stage configured to output a first stage output signal according to a result of comparing the pixel signal with the ramp signal, to a first circuit node; a limiter including an n-type transistor having one end connected to the first circuit node and an opposite end to which power supply voltage is applied; and a second comparator stage configured to generate the comparison result signal by shaping the first stage output signal.

An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.

An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.

A ramp generator includes a plurality of switched current sources coupled in parallel between a resistor and ground. A digital ramp control signal generator includes a counter to generate a ramp control signal in response to a clock signal. Each bit of the ramp control signal is coupled to control switching of a respective one of the plurality of switched current sources to generate a ramp signal at an output of the ramp generator. The digital ramp control signal generator is coupled to receive a reset signal to zero the ramp control signal. The digital ramp control signal generator is further coupled to receive a set bits signal to initialize the ramp signal to a preset value after every reset of the ramp control signal to add a DC offset compensation current determined by the preset value to the ramp signal.

Clock and other cyclical signals are driven onto respective capacitively-loaded segments of a distribution path via inverting buffer stages that self-correct for stage-to-stage duty cycle error, yielding a balanced signal duty cycle over the length of the distribution path.

There is provided a time measuring device including: a first counter unit (204) that acquires a difference time between a first measured signal and a second measured signal as a first measurement result by counting on the basis of a reference clock signal; a delay signal generation unit (208) that generates a delay signal by delaying the first measured signal on the basis of the first measurement result fed back from the first counter unit; a measurement unit (210) that measures a difference time between the delay signal and the second measured signal as a second measurement result; and an operation unit (212) that performs an operation by using the first measurement result and the second measurement result.

An imaging device of the present disclosure includes: a plurality of pixel circuits that each generates a pixel signal including a pixel voltage corresponding to an amount of received light, and performs AD conversion by comparing the pixel signal with a reference signal; and a reference signal generator including a signal generation circuit and a voltage follower circuit, the signal generation circuit that generates a voltage signal having a ramp waveform, and the voltage follower circuit that performs a voltage follower operation on the basis of the voltage signal to generate the reference signal, and supplies the reference signal to the plurality of pixel circuits.

Solid-state imaging elements that prevent deterioration of image quality, and reduce power consumption and AD-conversion time are disclosed. In one example, a solid-state imaging element includes a first comparator that uses a first voltage corresponding to an input voltage received from a first pixel, in reference to a first voltage difference between the input voltage and a first reference voltage, and that outputs a comparison result between the input voltage and the first reference voltage in reference to a second voltage difference, and a second comparator that outputs a comparison result of comparison between the input voltage and the second reference voltage in reference to a fourth voltage difference.

An image sensor includes a photoelectric conversion unit that photoelectrically converts incident light to generate an electric charge; and an AD conversion unit having a comparison unit that compares a signal caused by an electric charge generated by the photoelectric conversion unit with a reference signal, a first storage unit in a first circuit layer, the first storage unit storing a first signal based on a signal output from the comparison unit, and a second storage unit in a second circuit layer that is stacked on the first circuit layer, the second storage unit storing a second signal based on the signal output from the comparison unit.