An input circuitry for receiving an analog input signal comprises: an input transistor configured to receive the analog input signal on a gate terminal of the input transistor wherein the input transistor is connected to a digital component providing a digital signal, and wherein the input transistor is configured to receive the digital signal on a bulk terminal of the input transistor; wherein the input transistor is configured to provide an output current based on the analog input signal and the digital signal, such that the input transistor provides digital-to-analog conversion of the digital signal received on the bulk terminal.

An amplifier includes an input circuit configured to receive an analog input signal and a feedback signal, and output an analog error signal based on the analog input signal and the feedback signal. An ADC is configured to convert the analog error signal into a digital signal in a phase domain. A digital control circuit is configured to generate a digital control signal based on the digital signal in the phase domain. An output circuit is configured to generate an amplified output signal based on the digital control signal, and a feedback circuit is configured generate the feedback signal based on the amplified output signal.

A wide band continuous time delta-sigma modulator implements a time interleaved quantization processing operation. The modulator may provide for an inherent finite impulse response filtering in the feedback loop. Additionally, further finite impulse response filtering in each time interleaved feedback path may be provided.

During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

One example discloses a reconfigurable analog to digital converter (ADC) device, including: an analog front end (AFE) configured to receive a set of analog input signals and generate a corresponding set of digital output signals; wherein the AFE includes a set of reconfigurable ADC conversion circuits; and a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.

A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source.

A converter circuit includes an analog-to-digital signal conversion path. An input port receives an analog input signal having an offset, and an output port delivers a digital output signal quantized over M levels. The digital output signal is sensed by a digital-to-analog feedback path, which includes a digital-to-analog converter applying to the input port an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first and second states. M-bit digital word generation circuitry coupled to the digital-to-analog converter and sensitive to the two-state signal produces, alternately, during the first states, a first M-bit digital word, which is a function of the digital output signal quantized over M levels, and, during the second states, a second M-bit digital word, which is a function a correction value of the offset in the analog input signal.

The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample. The objective is also solved by a method using the aforementioned analog-to-digital converter.

A photoelectric conversion apparatus includes a light receiving circuit configured to convert light into an electrical signal, a readout circuit configured to read out an analog signal corresponding to the electrical signal, a ΔΣ A/D converter configured to convert the analog signal into a digital signal, and a control circuit configured to change a gain of the photoelectric conversion apparatus in accordance with a change of a driving mode of the photoelectric conversion apparatus. The analog signal read out by the readout circuit is an analog current signal. The readout circuit includes a variable resistor on a signal path for supplying the analog current signal to the ΔΣ A/D converter. The control circuit changes the gain of the photoelectric conversion apparatus by changing a resistance value of the variable resistor.

The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.